Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
1998-11-03
2002-01-08
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S537000, C327S543000
Reexamination Certificate
active
06337594
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a charge pump circuit, and more particularly, to a charge pump circuit which improves reliability and economic efficiency of a circuit.
2. Discussion of the Related Art
FIG. 1
is a circuit diagram illustrating a conventional charge pump circuit. As shown in
FIG. 1
, the conventional charge pump circuit includes an amplifier
11
, a condenser
12
, a first clock input
13
and a second clock input
14
. The amplifier
11
includes first, second, third, fourth and fifth NMOS transistors
15
,
16
,
17
,
18
and
19
connected in series. Gates and drains of the first, second, third, fourth and fifth NMOS transistors
15
,
16
,
17
,
18
and
19
are connected with one another, and their substrates are connected to a ground voltage VSS.
The drain of the first NMOS transistor
15
is connected to a driving voltage V
DD
, and the drain of the second NMOS transistor
16
is connected to a source of the first NMOS transistor
15
. In the same manner as the second NMOS transistor
16
, the drains of the third and fourth NMOS transistors
17
and
18
are respectively connected to sources of respective previous NMOS transistors.
The drain of the fifth NMOS transistor
19
is connected to the source of the fourth NMOS transistor
18
, and the source of the fifth NMOS transistor
19
is connected to an output
24
.
The condenser
12
includes first, second, third and fourth capacitors
20
,
21
,
22
and
23
. Each capacitor is formed by an NMOS transistor with the gate thereof serving as one electrode and the source, drain and substrate connected together serving as the other electrode. The first, second, third and fourth capacitors
20
,
21
,
22
and
23
are connected with gates and drains of the second, third, fourth, and fifth NMOS transistors
16
,
17
,
18
, and
19
, respectively.
The first and third capacitors
20
and
22
, connected to the drains of the second and fourth NMOS transistors
16
and
18
, are connected with the first clock input
13
. The second and fourth capacitors
21
and
23
, connected to the drains of the third and fifth NMOS transistors
17
and
19
, are connected with the second clock input
14
.
The operation of the aforementioned conventional charge pump circuit will be described below.
In the charge pump circuit, a voltage drop V
T
occurs when the first—fifth NMOS transistors
15
-
19
transfer a voltage at their drains to their sources because the same voltage at each respective drain is applied to the respective gate.
The driving voltage V
DD
is applied to the gate and drain of the first NMOS transistor
15
, so that the source of the first NMOS transistor
15
is charged to V
DD
−V
T
. In this state, if the first clock goes from 0V to V
DD
, the source of the first NMOS transistor
15
increases by V
DD
because the charge across the first capacitor
20
must remain constant. Accordingly, the charge at the source of the first NMOS transistor
15
is pumped to 2V
DD
−V
T
.
If 2V
DD
−V
T
is applied to the gate and drain of the second NMOS transistor
16
, the source voltage of the second NMOS transistor
16
becomes 2V
DD
−2V
T
. At this time, if the second clock
14
goes from 0V to V
DD
, the source voltage of the second NMOS transistor
16
increases by V
DD
and becomes 3V
DD
−2V
T
.
In the same manner as above, the operation at the third and fourth NMOS transistors
17
and
18
is performed.
Then, if 5V
DD
−4V
T
is applied to the gate and drain of the fifth NMOS transistor
19
, the source voltage of the fifth NMOS transistor
19
becomes 5V
DD
−5V
T
. Accordingly, an output voltage V
PP
of 5V
DD
−5V
T
appears at the output
24
. The output voltage V
PP
can be expressed as follows:
V
PP
=[V
DD
+n(V
CLK
−V
T
)]−V
T
(1)
assuming that both the first and second clocks transition by the same voltage V
CLK
, and where n is the number of pumping stages (i.e., the number of capacitors in the condenser
12
).
The conventional charge pump circuit has several problems.
First, because of the cummulative of the voltage drop V
T
occurring at each NMOS transistor in the amplifier
11
, a voltage lower than desired is output. This reduces the reliability of the circuit. In addition, more stages are required to output the desired voltage, but the additional stages reduce current driving ability and economic efficiency, in terms of size, of the circuit.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a charge pump circuit that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a charge pump circuit which compensates for the voltage drop to improve reliability and economic efficiency of a circuit.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
These and other objects are achieved by providing a charge pump circuit, comprising: an amplifier having a plurality of first voltage transfer stages, each first voltage transfer stage transferring a voltage from an input to an output thereof such that the output voltage equals the input voltage minus a voltage drop; a first condenser increasing the output voltage at the output of at least one of the voltage transfer stages; and voltage modifying means for modifying each increased output voltage to compensate for the voltage drop.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5029063 (1991-07-01), Lingstaedt et al.
patent: 5291446 (1994-03-01), Van Buskirk et al.
patent: 5422586 (1995-06-01), Tedrow et al.
patent: 5489870 (1996-02-01), Arakawa
patent: 5521547 (1996-05-01), Tsukada
patent: 5524266 (1996-06-01), Tedrow et al.
patent: 5589793 (1996-12-01), Kassapian
patent: 5818289 (1999-11-01), Chevallier et al.
patent: 5982223 (1999-11-01), Park et al.
Callahan Timothy P.
Hynix / Semiconductor Inc.
Nguyen Hai L.
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