Charge pump architecture

Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage

Reexamination Certificate

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Details

C327S536000, C327S437000

Reexamination Certificate

active

06747506

ABSTRACT:

BACKGROUND
Charge pumps are used to source current to or sink current from a load in response to control signals. Typically, these control signals consist of an UP signal and a DOWN signal. Current is sourced to the load in a case that the UP signal is active and the DOWN signal is inactive, and current is sunk from the load in a case that the UP signal is inactive and the DOWN signal is active. Ideally, no current flows through the load if both control signals are in the same state.
In a non-ideal charge pump, some current flows to or from the load if both control signals are in the same state. This current is known as leakage current. Leakage current may be reduced for a particular charge pump by tri-stating the output and/or increasing the output impedance of the charge pump.
A non-ideal charge pump also introduces delays into the system in which it is implemented. For example, many charge pumps employ switched current mirror structures. When a current is mirrored, the speed by which a current is switched through the mirror is limited by the device transit frequency of the transistors comprising the mirror. These delays may be significant in a case that the device transit frequency is similar to the phase detector comparison rate, which is the rate at which the charge pump control signals are updated. Hence, conventional charge pumps using switched current mirrors provide current matching at the expense of speed.
FIG. 1
illustrates a conventional differential charge pump that does not employ a current mirror. Charge pump
1
includes p-channel metal-oxide semiconductor (PMOS) transistor
2
. Transistor
2
receives voltage signal V
CMFB
from a common-mode feedback amplifier and generates a current which results in a stable common-mode voltage at the output of charge pump
1
.
A drain of transistor
2
is coupled to sources of PMOS transistor
3
and PMOS transistor
4
. Drains of transistors
3
and
4
are respectively coupled to drains of n-channel metal-oxide semiconductor (NMOS) transistor
5
and NMOS transistor
6
, and source terminals of transistors
5
and
6
are coupled to one another and to current source I
1
. These elements operate to generate differential output signal component OUT_N based on the differential charge pump control signals UP (composed of component signals UP and UPB) and DOWN (composed of DN and DNB). Charge pump
1
uses a second set of the above-described elements to generate differential output signal component OUT_P.
However, the components of the UP and DOWN differential control signals are applied to the second set of elements in a different arrangement.
Charge pump
1
therefore uses PMOS current switches stacked on NMOS current switches to steer the UP and DOWN signals to a load. These current switches require high output impedance because they are directly coupled to the output of charge pump
1
. This direct coupling also presents problems with signal feedthrough. Additionally, since the current switches are both PMOS and NMOS, charge pump
1
may require level shifting of the differential control signals. Level shifting may be required to allow for enough voltage dynamic range at the output of charge pump
1
. Yet another drawback of charge pump
1
is its use of local feedback, which complicates its design.


REFERENCES:
patent: 5598209 (1997-01-01), Cortjens et al.
patent: 5625306 (1997-04-01), Tada
patent: 5889437 (1999-03-01), Lee
patent: 6611160 (2003-08-01), Lee et al.

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