Charge pump and PLL

Details Charge pump and PLL Charge pump and PLL

2002-02-19

2003-01-21

Nuton, My-Trang (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

Reexamination Certificate

active

06509770

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a charge pump having an input side, an output side and having at least one current mirror and a transistor that are associated with a source branch for producing a source current and with a sink branch for producing a sink current. At least one path has an input-side transistor. Both paths contain an output stage with at least one output-side transistor and a circuit transistor. A first path is controlled via a reference current.
When using a phase locked loop (PLL), an oscillator VCO uses a highly accurate reference frequency to produce another highly accurate and stable frequency F
vco
that may be different from the original reference frequency. An illustrative circuit for such a PLL is shown in
FIG. 5
(described later). There, a (normally) crystal-stable frequency F
q
is divided down to a required reference frequency F
ref
using a frequency divider R. At the same time, the output frequency F
vco
of the voltage controlled oscillator VCO is divided down to a frequency F
vco
/N using a further frequency divider N. These two divided frequencies F
ref
and F
vco
/N are supplied to a phase(-frequency) detector PD, in which they are compared to give their relative phase, that is to say, to give a frequency change relative to one another. The output of the phase detector PD produces two pulse width modulated pulse trains UP and DOWN whose pulse widths have a fixed relationship with respect to the phase difference between the frequencies at its inputs.
If the frequency F
vco
/N is excessive in comparison with F
ref
, that is to say if the phase of the frequency F
vco
/N leads that of F
ref
, the phase detector switches on the DOWN output for longer than the UP output. The same applies in reverse; if the phase of the frequency F
vco
/N lags that of the frequency F
ref
, then the phase detector switches the UP output on for longer than the DOWN output. If the phases of the two input frequencies F
ref
and F
vco
/N in the phase detector PD are exactly the same, either no pulses or pulses of exactly the same length can be output to the two outputs of the phase detector PD on the UP and the DOWN output. If pulses of exactly the same length are output, reference is made to an “anti-backlash pulse” (ABL pulse). Producing these pulses when the phases are identical is more beneficial, from a dynamic point of view, than a circuit in which none of the two outputs is turned on when the phases are the same.
The UP and DOWN pulse trains actuate a charge pump CP having an output connected to a loop filter LF that acts like an integrator. This loop filter LF can be an active filter, or preferably, a passive filter in the phase locked loop.
A pulse on the UP line prompts the charge pump CP to feed a current of a defined magnitude into the loop filter LF, so that the voltage on the loop filter VLF rises over the duration of the UP pulse as a result of the quantity of charge that is transported into the loop filter. This action is called “sourcing” and is effected in the charge pump by the source branch.
A pulse on the DOWN line draws a current from the loop filter LF, so that the voltage tends to fall over the duration of the pulse. This action is called “sinking” and is effected by the sink branch in the charge pump.
The mean voltage change on the loop filter is thus determined, for currents of equal magnitude, exclusively by the relative durations of the UP and DOWN pulses with respect to one another. If the phases of the two input frequencies F
ref
and F
vco
/N on the phase detector are exactly the same, that is to say when the anti-backlash pulse occurs, the voltage on the loop filter LF ideally should not change, since the net current into the loop filter is equal to zero, and also since no net quantity of charge is transported into the loop filter or away from the loop filter.
The voltage v_tune that is established on the loop filter LF at the output V
lf
is now used as a control voltage for the oscillator VCO, whose frequency F
vco
or whose phase is coupled to the phase of the crystal oscillator Q by the control loop that is now connected. Altering the division ratio of the divider N allows the oscillator frequency F
vco
to be adjusted over broad ranges.
However, for this purpose, it is necessary to vary the control voltage for the oscillator, which is the same as the voltage v_tune at the output V
lf
of the loop filter LF, over a broad range to be able to keep the voltage controlled oscillator VCO at the desired frequency. Ideally, this means that the voltage range used needs to come close to the zero potential and close to the supply voltage. This is important particularly for portable applications, since in that case the supply voltage from the storage batteries available is in the region of 3 volts. In this context, it is also important for the source and sink current magnitudes to be kept at the same level, since only then, when the phase locked loop has locked during the ABL pulse, is no net charge transported, and the oscillator VCO, therefore is not detuned.
FIG. 1
shows an example of a prior art charge pump circuit configuration. The charge pump has a source branch including PMOS transistors mp
1
, mp
2
, mp
3
, and mp
4
that are connected as a current mirror that multiplies the current i_ref_source by a prescribed mirror ratio n and feeds it from the voltage supply VDD into the output connection Pdout providing the voltage v_tune as soon as the UP control signal has a logic LOW potential. The UP control input has the inverted UP signal of the phase detector PD applied to it.
In addition, this known charge pump has a sink branch that is arranged in a mirror-inverted form with respect to the source branch, and in line with its function, is equipped with NMOS transistors mn
1
, mn
2
, mn
3
, and mn
4
which, during a logic HIGH potential on the DOWN control connection, conduct the current i_ref_sink multiplied by the prescribed mirror ratio n away from the output connection Pdout in the direction of ground VSS.
In this circuit configuration, the problem arises that the mirror ratios in the source branch and in the sink branch can be adjusted exactly symmetrically only at a single voltage v_tune at the output Pdout, at a particular operating temperature and for particular circumstances of technological parameters (for example output impedance of the transistors, threshold voltage V
T
or matching). The channel length modulation in the MOS transistors, the technological variations (for example matching), and the temperature response of the electronic components mean that the currents i_source and i_sink are asymmetrical at all other voltages v_tune. Thus, for example, the transistor output impedance means that, for a rising voltage v_tune, the magnitude of the sink current becomes greater and the magnitude of the source current become less, whereas, with a falling voltage v_tune, the source current i_source becomes larger and the sink current i_sink becomes smaller.
For v_tune values close to VDD or Gnd, the output transistors mp
1
and mn
1
are additionally no longer operated in the (low) saturation region, which means that a noticeable reduction in the source and sink currents ensues.
In a practical implementation, this means, by way of example, that the source current i_source decreases dramatically from voltage values VDD−0.4 V upward and is finally 0 when v_tune=VDD. The same applies to the sink current i_sink, which is dramatically reduced from approximately 0.4 V downward and finally likewise becomes 0 at the voltage v_tune=0V. In practice, this means that a fault current “i_fault” is produced between the source branch and the sink branch when the source and sink sections are active at the same time. This fault current thus rises extremely at the upper and lower limits of the supply voltage, and when v_tune=VDD, results in the fault current becoming equal to the sink current i_sink, since the source current i_source becomes equal to 0, and conversely, the fault curr

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