Charge neutralization using silicon-enriched oxide layer

Details Charge neutralization using silicon-enriched oxide layer Charge neutralization using silicon-enriched oxide layer

1990-03-05

1991-10-15

James, Andrew J.

357 49, 357 52, 357 71, H01L 2934

Patent

active

050578979

ABSTRACT:
Parasitic leakage is minimized in a MOS structure. An integrated circuit wafer comprises conventional MOS elements as applied through a first level metallization. An intermetal dielectric includes three layers, an intermediate organic glass layer used for planarization and upper and lower oxide layers. A second metallization is applied over the dielectric. Passivation includes a lower oxide passivation and an upper nitride passivation. Hydrogen from the nitride passivation migrates into the organic glass and forms positive charges that induce the parasitic leakage. The lower oxide layer in the intermetal dielectric is silicon-enriched to provide dangling bonds which neutralize this charge formation and thus minimize the parasitic leakage.

REFERENCES:
patent: 4123565 (1978-10-01), Sumitomo et al.
patent: 4502202 (1985-03-01), Malhi
patent: 4613888 (1986-09-01), Mase et al.
Yoshida, S., "Improvement of Endurance to Hot Carrier Degradation . . . " IEDM 1988 pp. 22-25.

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