Charge mode open/short test circuit

Details Charge mode open/short test circuit Charge mode open/short test circuit

1998-07-02

2000-08-01

Hoff, Marc S.

Data processing: measuring, calibrating, or testing

Testing system

Of circuit

702108, 702117, 324519, 324537, 324754, G01R 3102

Patent

active

060980273

ABSTRACT:
A charge mode open/short test circuit comprises at least two charge capacitors. A plurality of signal traces under test are connected to the test circuit first through a plurality of test tips on a test prober and then a plurality of transmission gates in a test circuit. In a load mode, reference data are loaded. In a test mode, a charge capacitor is sequentially selected and discharged into the parasitic capacitor corresponding to a sequentially selected signal trace under test for generating a charge balance signal. The signal is amplified and compared with the loaded reference data in either a digital or an analog manner. The compared pass/fail output related to the property of the signal trace is stored in a memory. In a following read mode, the stored pass/fail output is read out to an external unit for further processing.

REFERENCES:
patent: 4583042 (1986-04-01), Riemer
patent: 4734651 (1988-03-01), Keller et al.
patent: 5744964 (1998-04-01), Sudo et al.

Affiliated with

Also associated with

Rating

Charge mode open/short test circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Charge mode open/short test circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Charge mode open/short test circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-673198