Charge loss compensation during programming of a memory device

Details Charge loss compensation during programming of a memory device Charge loss compensation during programming of a memory device

2011-08-09

2011-08-09

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185220, C365S185170

Reexamination Certificate

active

07995395

ABSTRACT:
A selected memory cell on a selected word line is programmed through a plurality of programming pulses that are incremented by a step voltage. After a successful program verify operation, programming of the selected memory cell is inhibited while other memory cells of the selected word line are being programmed. Another program verify operation is performed on the selected memory cell. If the program verify operation fails, a bit line coupled to the selected cell is biased at the step voltage and a final programming pulse is issued to the selected word line. The selected memory cell is then locked from further programming without evaluating the final program verify operation.

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patent: 2007/0047318 (2007-03-01), Nagai et al.
patent: 2007/0230250 (2007-10-01), Chan

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