Charge generation of solid state image pickup device

Television – Camera – system and detail – Solid-state image sensor

Reexamination Certificate

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Reexamination Certificate

active

06778214

ABSTRACT:

This application is based on Japanese patent applications No. 10-69454 filed on Mar. 4, 1998, and No. 10-150730 filed on May 14, 1998, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
a) Field of the Invention
The present invention relates to a solid state image pickup device capable of storing an increased amount of signal charges in each light reception element, the solid state image pickup device being of the type that signal charges stored in light reception elements are read to form a frame image through interlace drive.
b) Description of the Related Art
A charge coupled solid state image pickup device (hereinafter called a CCD image pickup device) of an interline transfer type is known. As shown in
FIG. 7A
, this CCD image pickup device is constituted of: a number of photodiodes (light reception elements) PD
1,1
, to PD
I,J
disposed in a matrix (rows and columns) layout; vertical transfer paths VCT
1
to VCT
J
juxtaposed with the photodiodes PD
1,1
to PD
I,J
via transfer gates TG
1,1
to TG
Ij
; a horizontal transfer path HCT connected at one ends of the vertical transfer paths VCT
1
to VCT
J
; and an output circuit OUT connected to at one end of the horizontal transfer path HCT.
The vertical transfer paths VCT
1
to VCT
J
vertically transfer signal charges photo-excited and stored in the photodiodes PD
1,1
to PD
I,J
in response to four-phase drive signals V
1
to V
4
synchronizing with a signal representative of one horizontal scan period. The horizontal transfer path HCT horizontally transfers the signal charges transferred from the vertical transfer paths VCT
1
to VCT
J
in response to two-phase drive signals H
1
and H
2
synchronizing with a signal representative of one horizontal blanking period. By repeating such vertical and horizontal transfer operations, the output circuit OUT outputs a pixel signal Vout of one frame.
Of the photodiodes PD
1,1
to PD
I,J,
those on odd rows are assigned an odd field, and those on even rows are assigned an even field. With an interlace drive using a vertical transfer by the four-phase drive signals V
1
to V
4
and a horizontal transfer by the two-phase drive signals H
1
and H
2
, two fields of an odd field and an even field are read to output the pixel signal Vout of one frame.
The interlace drive is executed synchronously with four-phase drive signals V
1
to V
4
such as shown in FIG.
7
B. Potential profiles of the transfer gates TG
1,1
to TG
I,J
and vertical transfer paths VCT
1
to VCT
J
change synchronously with the four-phase drive signals V
1
to V
4
, as shown in FIGS.
8
AA to
8
EB, in order to read odd and even fields.
In reading signal charges Q
O
of the odd field shown hatched, the potential profiles change as shown in FIGS.
8
AA,
8
BA,
8
CA,
8
DA, and
8
EA. In reading signal charges Q
E
of the even field shown hatched, the potential profiles change as shown in FIGS.
8
AB,
8
BB,
8
CB,
8
DB, and
8
EB. In FIGS.
8
AA to
8
EB, the abscissa represents a horizontal direction in FIG.
7
A and the ordinate represents a potential. The photodiodes and transfer gates of the odd field are represented by PD
O
and TG
O
, respectively. The photodiodes and transfer gates of the even field are represented by PD
E
and TG
E
, respectively. Each or all of the vertical transfer paths VCT
1
to VCT
J
are represented by VCT where applicable.
During an exposure period &tgr;
ON
shown in
FIG. 7B
, all channel potentials (hereinafter called channel barriers) under the transfer gates TG
O
and TG
E
are made high as shown in FIGS.
8
AA and
8
AB so that photo-excited signal charges Q
O
and Q
E
corresponding in amount to an object illuminance h&ngr; are stored in all photodiodes PD
O
and PD
E
.
At a timing t
1
after the exposure period &tgr;
ON
, the drive signal V
1
which is a pulse PL
1
having a level higher than a predetermined threshold voltage Vth is applied to the transfer gates TG
O
of the odd field. Therefore, as shown in FIG.
8
BA, only the channel barriers under the transfer gates TG
O
are made low so that only the signal charges Q
O
of the photodiodes PD
O
are transferred to the vertical transfer paths VCT. As shown in FIG.
8
BB, the signal charges Q
E
in the photodiodes PD
E
are not transferred to the vertical transfer paths VCT but are stored in the photodiodes PD
E
.
During an odd field read period &tgr;
1
(FIG.
7
B), the vertical transfer paths VCT
1
to VCT
J
vertically transfer the transferred signal charges Q
O
in synchronization with the four-phase drive signals V
1
to V
4
, and the horizontal transfer path HCT horizontally transfers the vertically transferred signal charges Q
O
and outputs the pixel signal Vout corresponding to the odd field. The potential profiles during the odd field read period &tgr;
1
are as shown in FIGS.
8
CA and
8
CB. The potential profile shown in FIG.
8
CB will be later detailed.
At a timing t
2
after the odd field read period &tgr;
1
, the drive signal V
3
which is a pulse PL
3
having a level higher than the predetermined threshold voltage Vth is applied to the transfer gates TG
E
of the even field. Therefore, as shown in FIGS.
8
DA and
8
DB, only the channel barriers under the transfer gates TG
E
are made low so that only the signal charges Q
E
of the photodiodes PD
E
are transferred to the vertical transfer paths VCT.
During an even field read period &tgr;
2
, the vertical transfer paths VCT
1
to VCT
J
vertically transfer the transferred signal charges Q
E
in synchronization with the four-phase drive signals V
1
to V
4
, and the horizontal transfer path HCT horizontally transfers the vertically transferred signal charges Q
E
and outputs the pixel signal Vout corresponding to the even field. The potential profiles during the even field read period &tgr;
2
, are as shown in FIGS.
8
EA and
8
EB.
As above, the pixel signals of one frame can be read by reading two fields during the odd field read period &tgr;
1
and even field read periods &tgr;
2
.
The conventional CCD image pickup device is, however, associated with some problem which is caused by reading the pixel signals of one frame from two fields, at different timings.
With th conventional CCD image pickup device, the signal charges in the photodiodes PD
E
of the even field are read during the even field read period &tgr;
2
after the odd field read period &tgr;
1
. However, as shown in FIG.
8
CB, during the odd field read period &tgr;
1
, the signal charges Q
E
leak to the semiconductor substrate so that the signal charge amount in the photodiode PD
E
reduces more than the signal charge amount photo-excited and stored therein the exposure period &tgr;
ON
.
This leak phenomenon may be ascribed to thermal emission of signal charges in the photodiode PD
E
, because of the thermal emission, the signal charges passing over the potential barrier between the photodiode PD
E
and semiconductor substrate and flowing toward the semiconductor substrate. A current I converted from the charge amount leaked from the photodiode PD
E
to the semiconductor substrate is theoretically expressed by:
I
∝ exp(−
qVbar/kT
)
where Vbar is a potential of the potential barrier, q is a signal charge, k is the Voltzmann's constant, and T is an absolute temperature.
The signal charges in the photodiode PD
O
are rarely subject to the leak phenomenon, because they are read first during the odd field read period &tgr;
1
. On the other hand, the signal charges in the photodiode PD
E
are influenced by the leak phenomenon, because they are stored until the odd field read period &tgr;
1
finishes and they are leaked during this store period.
Therefore, an amount (hereinafter called a saturated charge amount) of signal charges capable of being stored in the photodiode PD
O
of the odd field becomes substantially different from a saturated charge amount of signal charges capable of being stored in the photodiode PD
E
of the even field, resulting in a difficulty of forming a clear frame image. This problem becomes conspicuous when a stil

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