Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
1999-12-22
2001-07-10
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S143000, C327S198000
Reexamination Certificate
active
06259284
ABSTRACT:
FIELD
The invention relates to a CMOS integrated circuit, more particularly, a time delay circuit including a voltage discharging circuit which allows a capacitor to be more fully discharged, thereby reducing the capacitance needed to achieve a desired RC time constant.
BACKGROUND
In complementary metal oxide silicon (CMOS) structures a well known parasitic effect occurs between a pair of cross-coupled parasitic pnp and npn bipolar transistors which form a positive feedback path. The current gain in the two transistors can reach a point in which a circuit is easily triggered by an external disturbance such that it creates a regenerative condition and the transistors are driven by each other. The current in both transistors can increase until they self limit or until they lead to the destruction of an integrated circuit. This condition, known as latch-up, can occur when a back bias generator is contained in an integrated circuit and the integrated circuit is powered on. During power-on, the back bias generator voltages are not clearly defined, the well regions are not biased to the correct levels, and hence under such conditions latch-up is likely to occur. The back bias generator is useful, however, during integrated circuit stand-by mode when it reduces the transistor subthreshold current by applying a bias voltage to the well regions to establish greater threshold voltages than during the active mode of operation. For example, in modem deep sub-micron process technology, MOS transistor threshold voltage is usually in the range of 0.25 volts to 0.4 volts. With such threshold voltage and leakage worst operating condition (e.g., high temperature and fast process comer), transistor drain leakage at its off state can occur in the range of several tens of nano-amperes per unit size. The total leakage can increase to a problematic level, especially in battery-powered applications, with the use of many transistors (i.e., for an integrated circuit such as microprocessor, the total leakage of hundreds of mA can occur). Therefore, the back bias generator is used to bias the well regions to increase the threshold voltage, significantly reducing transistor leakage during standby mode.
It is common practice to use a resistor
11
and a capacitor
12
in series, as shown in
FIG. 1
a
, to provide an RC time constant which determines the amount of time required to reach a desired capacitor voltage on output terminal
13
from an applied source voltage on line
14
. This type of resistor-capacitor (RC) circuit
10
is used to disable the back bias generator and force the integrated circuit into the active mode when the integrated circuit is initially powered on (i.e., “power on reset”). Capacitor
12
charges through resistor
11
when VDD is applied to the integrated circuit and discharges through resistor
11
when VDD is removed. RC circuit
10
provides an output terminal
13
, a power-on-reset control signal according to the voltage versus time characteristics as shown in
FIG. 1
b
. The problem with this prior art circuit is that a high value multi-mega ohm resistor
11
is necessary to obtain the desired RC time constant. This type of resistor is often unavailable in many types of fabrication processes.
A second prior art circuit widely used but still having shortcomings that are overcome by the present invention is shown in
FIG. 2
a
. Here, PMOS transistor
21
, having a long and thus highly resistive channel, is used in place of high resistance resistor
11
of
FIG. 1
a
. When VDD is applied to lead
24
, P channel transistor
21
turns on, charging capacitor
22
, providing the power-on-reset signal shown in
FIG. 2
b
. When VDD is removed from lead
24
, capacitor
22
discharges to lead
24
through transistor
21
(now the drain and source reversed) and the PN junction formed between drain
21
c
and the well region of transistor
21
. However, the discharging of capacitor though the PN junction stops when the voltage on capacitor
22
drops below the diode turn-on voltage and the discharging of capacitor
22
through transistor
21
stops when the voltage on capacitor
22
drops below threshold voltage of transistor
21
. This is shown in the diagram of
FIG. 2
b
. When VDD is switched on and the voltage on capacitor
22
is not zero, capacitor
22
charging time is severely decreased. Thus, the capacitance of capacitor
22
must be significantly increased to assure the desired RC time constant to provide an appropriate time period upon power-on-reset during which the back bias generator is disabled and the integrated circuit is placed in the active mode, thereby preventing latch-up. To assure the desired RC time constant using this circuit which provides the power-on-reset signal on output terminal
23
, a large capacitance is needed. However, using a large capacitor increases the integrated circuit area and is thus expensive.
SUMMARY
In accordance with the teachings of this invention a novel structure and method are taught for fully discharging a capacitor and thereby reducing the capacitance needed to achieve a desired RC time constant. The invention overcomes the previously encountered problem of using a large and area-inefficient capacitor. The invention allows for conservation of integrated circuit space and is cost effective.
REFERENCES:
patent: 4716322 (1987-12-01), D'Arrigo et al.
patent: 4797584 (1989-01-01), Aguti
patent: 5321317 (1994-06-01), Pascucci et al.
patent: 5612641 (1997-03-01), Sali
patent: 5828251 (1998-10-01), Freyman et al.
patent: 5898327 (1999-04-01), Tanaka
patent: 5999039 (1999-12-01), Holst et al.
patent: 05014158A (1993-01-01), None
patent: 11145808A (1999-05-01), None
Clements, Alan,Microprocessor System Design: 68000 Hardware, Software and Interfacing,1992, 2nded., PWS-Kent Publishing Company, pp. 147-162.
Hwang Changku
Miyazaki Masayuki
Mizuno Hiroyuki
Caserza, Esq. Steven F.
Dinh Paul
Flehr Hohbach Test Albritton & Herbert LLP
Hitachi America Ltd.
Wells Kenneth B.
LandOfFree
Charge free power-on-reset circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Charge free power-on-reset circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Charge free power-on-reset circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2491494