Charge domain filter circuit

Details Charge domain filter circuit Charge domain filter circuit

2011-04-26

2011-04-26

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

Unwanted signal suppression

C327S094000, C327S231000, C327S241000, C327S355000, C327S361000

Reexamination Certificate

active

07932773

ABSTRACT:
A charge domain filter circuit includes a first signal output portion, at least one second signal output, portion, a third signal output portion, and an adder portion. The first signal output portion outputs a first signal that is sampled at a specified time interval. Each second signal, output portion outputs a second signal that is sampled after a specified delay after the first signal is sampled. Where a plurality of the second signal output portions is included, the second signals are sampled in succession. The third signal output portion outputs a third signal that is sampled after a specified delay after the last second signal is sampled. The adder portion adds the first, second, and third signals together and outputs the result. The capacitance ratio of the sampling capacitors in the first signal output portion and the second signal output portion is one of continuously or discretely varied.

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R. Bagheri et al., “An 800 MHz to 5 GHz Software-Defined Radio Receiver in 90 nm CMOS,” in IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 480-481 (2006).
H. Repo et al., “Programmable switched capacitor 4-tap FIR filter”, XP010677425, European Solid-State Circuits, pp. 445-448 (2003).
J. Gan et al, “A Non-Binary Capacitor Array Calibration Circuit with 22-bit Accuracy in Successive Approximation Analog-to-Digital Converters” XP010635277, The 2002 45thMidwest Symposium on Circuits and Systems. Coference Proceedings, IEEE, U.S., vol. 1, pp. I-567-570 (2002).
European Search Report dated Nov. 4, 2009, in EP 08 25 3722.

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