Charge domain block matching processor

Details Charge domain block matching processor Charge domain block matching processor

1990-07-11

1991-07-09

Pellinen, A. D.

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

364602, 358105, 365 49, 365183, H03M 700, G06J 100

Patent

active

050309536

ABSTRACT:
A full search block matching algorithm includes a charge-domain serial tapped delay line as an input buffer, and an array of charge domain signal processors. The delay line shifts and holds analog sampled data which are in the form of charge packets. At each stage of delay, the signals are nondestructively sensed and coupled to a corresponding signal processor, and the sampled data are transferred and subsequently processed in parallel. The processed data from all the processors can be read out either in a parallel or serial format through a parallel-in-serial-out output buffer. In this structure, only the serial input buffer has to be clocked at the system throughout rate; the internal clock rate of each processor is reduced by the number of parallel processors. Within each processor, all of the computation functions are performed in the charge domain, and local charge domain memories are included for storing the processed signal.

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patent: 4760558 (1988-07-01), Berger
patent: 4922452 (1990-05-01), Larsen et al.

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