Charge domain bit serial vector-matrix multiplier and method the

Details Charge domain bit serial vector-matrix multiplier and method the Charge domain bit serial vector-matrix multiplier and method the

1990-05-14

1993-11-02

Smith, Jerry

Boots, shoes, and leggings

364807, 364862, 364844, G06G 716, G06J 712

Patent

active

052589340

ABSTRACT:
A charge domain bit serial vector matrix multiplier for real time signal processing of mixed digital/analog signals for implementing opto-electronic neural networks and other signal processing functions. A combination of CCD and DCSD arrays permits vector/matrix multiplication with better than 10.sup.11 multiply accumulates per second on a one square centimeter chip. The CCD array portion of the invention is used to load and move charge packets into the DCSD array for processing therein. The CCD array is also used to empty the matrix of unwanted charge. The DCSD array is designed to store a plurality of charge packets representing the respective matrix values such as the synaptic interaction matrix of a neural network. The vector multiplicand may be applied in bit serial format. The row or sensor lines of the DCSD array are used to accumulate the results of the multiply operation. Each such row output line is provided with a divide-by-two/accumulate CCD circuit which automatically compensates for the increasing value of the input vector element's bits from least significant bit to most significant bit. In a similar fashion each row output line can be provided with a multiply-by-two/accumulate CCD circuit which automatically accounts for the decreasing value of the input vector element's bits from most significant bit to least significant bit. The accumulated charge packet output of the array may be preferably converted to a digital signal compatible with the input vector configuration by utilizing a plurality of analog-to-digital converters.

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Semi-Parallel Microelectronic Implementation of Neural Network Models Using CCD Technology, Electronics Letters, vol. 23, No. 11, pp. 580-581, May 21, 1987.
Parallel Optoelectronic Realization of Neural Network Models Using CID Technology, Applied Optics, vol. 27, p. 4354, Nov. 1 1988.
A 100MS 16-Point CCD Cosine Transform Procesor by Chiang et al, p. 306 of the technical papers of the Feb. 27, 1987 IEEE International Solid-State Circuits Conference.

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