Charge dissipation in capacitively loaded ports

Details Charge dissipation in capacitively loaded ports Charge dissipation in capacitively loaded ports

1995-04-17

1996-08-13

Tran, Toan

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Signal transmission integrity or spurious noise override

327380, 327170, 327111, 326 21, H03K 1716, H03K 512

Patent

active

055460399

ABSTRACT:
A cascade of triggering circuits sequentially activates a series of parallel pull-down paths in reflexive response to a pull-down signal indicating correspondence between the potential on a capacitively loaded port and a selectable threshold voltage. The triggering circuits are clocked with a common signal to sequentially propagate the pull-down signal from prior to subsequent triggering stages to sequentially activate corresponding parallel paths. In a preferred embodiment, the D flip-flops of a sequential cascade control multiple pull-down paths to regulate charging and discharging of a joystick capacitive load on a monolithic audio personal computer IC game port. To initiate charging of the joystick capacitor, the flip-flops simultaneously disable the pull-down paths in response to a system WRITE signal. To discharge the joystick capacitor, the flip-flops sequentially propagate a comparator derived pull-down signal to sequentially enable the pull-down paths to controllably dissipate the accumulated charge.

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patent: 5218239 (1993-06-01), Boomer
patent: 5306965 (1994-04-01), Asprey
patent: 5495199 (1996-02-01), Hirano

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