Charge coupled semiconductor device storing 2-bit information

Details Charge coupled semiconductor device storing 2-bit information Charge coupled semiconductor device storing 2-bit information

1978-04-28

1981-01-06

Munson, Gene M.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

357 24, G11C 1928, H01L 2978

Patent

active

042438977

ABSTRACT:
The single input gate electrode in a conventional CCD shift register is replaced by four spaced electrodes. The fourth electrode adjacent to the first transfer electrode has an area larger than that of the second electrode which always has a DC voltage applied thereto. Three driving pulses are applied in a predetermined sequence to the first, third and fourth electrodes while the two bit values of 2-bit information are written into the register and a charge is accumulated directly under the fourth input gate electrode at one of four levels as determined by the combination of the write bit values. Then the accumulated charge is stepwise transferred in the same manner as in conventional CCD shift registers.

REFERENCES:
patent: 3935477 (1976-01-01), Strain et al.
patent: 4080581 (1978-03-01), Sakaue et al.
patent: 4085459 (1978-04-01), Hirabayashi
patent: 4112456 (1978-09-01), Lampe et al.
Sequin et al., Charge Transfer Devices, Academic Press, N.Y. (1975), pp. 23-25, 48-51, 62-65.
Mohsen et al., "A 64-Kbit Block Addressed Charge-Coupled Memory," IEEE Trans. Electron Devices, vol. ED-23 (2/76), pp. 117-126.
Rosenbaum et al., "A 1638-Bit High-Density CCD Memory," IEEE Trans. Electron Devices, vol. ED-23 (2/76, pp. 101-108.
Kohyama et al., "A New Multiphase Electrode-Per-Bit Structure for CCD Memory," Proc. 8th Conf. (1976 Int.), Solid State Devices, Japanese J. Applied Physics, vol. 16 (1977), Supple. 16-1, pp. 383-386.

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