Charge coupled EEPROM device and corresponding method of...

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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C365S185080, C365S185140, C365S185180, C365S185270, C257S318000, C257S320000, C257S322000, C257SE21421

Reexamination Certificate

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10482682

ABSTRACT:
This invention provides a semiconductor memory device and a corresponding method of operation. The semiconductor memory device comprises a semiconductor substrate having a first conductivity; a plurality of gate structures for storing charge in a non-volatile manner regularly arranged in above the surface of the semiconductor substrate and electrically isolated therefrom; a plurality of wordlines, each of the gate structures being connected to one of the wordlines and a group of the gate structures being connected to a common wordline; and a plurality of active regions, each of the active regions being individually connectable to at least one of the gate structures.

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patent: 57005362 (1982-01-01), None
S.K. Lahiri, “MNOS/Floating-Gate Charge Coupled Devices for High Density EEPROMS: A New Concept,” Physics of Semiconductor Devices, vol. 3316, No. 2, pp. 951-956, XP001035171.
Patent Abstracts of Japan, vol. 006, No. 064, Apr. 23, 1982, & JP 57 005362 A, Jan. 12, 1982, Abstract.

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