Charge coupled devices having narrow coplanar silicon electrodes

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357 59, H01L 2978, H01L 2904

Patent

active

046368264

ABSTRACT:
In a semiconductor device, for example a SPS memory having narrow coplanar silicon electrodes, the electrodes are formed by etching grooves or slots having a width in the submicron range into a polycrystalline silicon layer with the slot width being defined by the oxidized edge of a silicon auxiliary layer. The electrodes are alternately covered by silicon oxide and by a layer comprising silicon nitride. The covered electrodes are first interconnected pairwise, whereupon they are separated from each other, and are provided with self-aligned contact windows. Thus, the very narrow electrodes can be contracted without technological problems and memory cells of very small dimensions are provided.

REFERENCES:
patent: 4055885 (1977-11-01), Takemoto
patent: 4063992 (1977-12-01), Hosack
patent: 4352237 (1982-10-01), Widmann

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