Charge-coupled device with varible storage capacity and constant

Details Charge-coupled device with varible storage capacity and constant Charge-coupled device with varible storage capacity and constant

1988-04-19

1989-09-19

Ng, Jin F.

Facsimile and static presentation processing

Facsimile

Recording apparatus

35821325, H04N 314

Patent

active

048686654

ABSTRACT:
In a one-electrode/bit SPS CCD memory, a capacity reduction can be obtained by phase shift of one or more clock voltages. For an n-phase system with N groups of n electrodes, the storage capacity can thus be reduced stepwise from at most N(n-1) bits to N(n-2) bits, etc. The stay time of the bits stored is reduced by a corresponding factor, as a result of which the clock frequency in the series registers need not be changed. By this reduction, the memory is more particularly suitable for storing television pictures both in the 625 lines system and in the 525 lines system.

REFERENCES:
patent: 4426664 (1984-01-01), Nagumo et al.
patent: 4656520 (1987-04-01), Hurst
patent: 4731656 (1988-03-01), Dischert et al.

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