Charge coupled device staircase electrode multiplexer

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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357 24, 365183, G11C 1928, H01L 2978

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active

043061605

ABSTRACT:
A charge coupled device multiplexed parallel channel storage array useful with a serial input register having a storage density unconstrained by the serial register and effective for storing analog information. The same serial register cell reads charge packets sequentially to successive parallel channels by means of a single multiplexer electrode overlying the entrances to the parallel channels in a staircase configuration to which the entrances themselves conform.

REFERENCES:
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patent: 3967254 (1976-06-01), Kosonocky et al. 357
patent: 4056737 (1977-11-01), Sequin
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patent: 4199691 (1980-04-01), Angle
patent: 4211936 (1980-07-01), Kosonocky et al.
Kohyama et al., "A New Multiplexed Electrode-Per-Bit Structure for a 64-KBit Charge Coupled device Memory" J. Solid-State Circuits vol. SC-12 (8/77) pp. 335-343.
Sequin et al., Charge Transfer Devices Academic Press, N.Y. (1975) pp. 243-249.

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