Charge coupled device delay line employing a floating gate or fl

Details Charge coupled device delay line employing a floating gate or fl Charge coupled device delay line employing a floating gate or fl

1992-01-23

1993-07-13

James, Andrew J.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Charge transfer device

257221, 257236, H01L 2978, H01L 2702

Patent

active

052276503

ABSTRACT:
The present invention is to provide a CCD delay line in which a deterioration of a charge transfer efficiency can be reduced by maintaining a charge amount treated in a charge transfer section provided at the rear stage of an intermediate output section. According to an aspect of the present invention, in a charge transfer device having charge transfer sections of a plurality of stages consisting of electrode pairs of a transfer gate electrode and a storage gate electrode and at least one intermediate output section provided at the rear stage of a charge transfer section of a predetermined stage from the signal input side, a cross-sectional area of at least one of the transfer gate electrode and the storage gate electrode in the charge transfer section provided at the rear stage of the intermediate output section is selected to be larger than that in the charge transfer section provided at the front stage of the intermediate output section. Further, the impurity concentration in the region of a semiconductor substrate corresponding to the transfer gate electrode in the charge transfer section provided at the rear stage of the intermediate output section is selected to be lower than that in the charge transfer section provided at the front stage of the intermediate output section, thereby the potential barrier being increased.

REFERENCES:
patent: 4513431 (1985-04-01), Chamberlain et al.
patent: 4594604 (1986-06-01), Kub

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