Charge coupled device

Details Charge coupled device Charge coupled device

1998-12-29

2002-05-07

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making device or circuit responsive to nonelectrical signal

Responsive to electromagnetic radiation

C438S075000, C438S078000

Reexamination Certificate

active

06383834

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a charge coupled device (CCD) and, more particularly, to a CCD and method of fabricating the same, which reads signal charges completely and increases the fill factor of its pixel, to improve the sensitivity.
2. Discussion of Related Art
A conventional CCD is constructed in such a manner that photodiodes are arranged in matrix form, and vertical charge coupled devices (VCCDs), which receive charges accumulated in the photodiodes and transmit them to horizontal charge coupled devices (HCCDs) are formed in a row between the photodiodes. At present, a 4-phase VCCD using triple polysilicon layers is employed as the vertical charge transfer region of quarter-inch three hundred thirty thousand square pixel progressive scan CCDs (PS-CCDs). A conventional CCD having the 4-phase VCCD structure using the triple polysilicon layers and method of fabricating the same are explained below with reference to the attached drawings.
FIG. 1
is a plan view of the conventional CCD using the 4-phase VCCD structure of triple polysilicon layers,
FIG. 2A
is a cross-sectional view of the conventional VCCD, taken along line
2
a
—
2
a
of
FIG. 1
,
FIG. 2
b
is a cross-sectional view of the conventional CCD, taken along line
2
b
—
2
b
of
FIG. 1
, and
FIG. 2
c
is a cross-sectional view of the conventional CCD, taken along line
2
c
—
2
c
of FIG.
1
.
FIG. 3
show readout clocks of the conventional CCD, and
FIGS. 4
a
to
4
d
are cross-sectional views showing a method of fabricating the conventional CCD.
Referring to
FIGS. 1
,
2
a
,
2
b
and
2
c
, the conventional CCD is constructed in such a manner that a P-well
2
is formed in an N-type semiconductor substrate
1
to a predetermined depth, and a buried charge coupled device (BCCD)
3
is formed in P-well
2
in the direction of VCCD. A first interlevel oxide layer
6
is formed over the substrate
1
. The first transfer gates
7
, formed of a first polysilicon layer, are formed in parallel in the row direction, at a specific interval on the first interlevel oxide layer
6
. The first interlevel oxide layer
6
and the first transfer gates
7
are formed between photo diodes
4
, and a portion of each is formed on the BCCD
3
. A block oxide layer
8
is formed on a portion of the first transfer gate
7
, and a second interlevel oxide layer
9
is formed to cover the remaining portions of the first transfer gate
7
. Second and third transfer gates
10
a
and
10
b
are superposed on both edges of each first transfer gate
7
, the gap region between photodiodes
4
and the first transfer gate
7
in the row direction, on the edges of the photodiodes
4
, and a region of the BCCD
3
. The second and third transfer gates
10
and
10
b
are also arranged in parallel. A third interlevel oxide layer
12
is formed to cover the second and third transfer gates
10
a
and
10
b
. A fourth transfer gate
13
a
is formed over the first transfer gate
7
between the photodiodes
4
, and is partially superposed on the second transfer gate
10
a
, the third transfer gate
10
b
, the BCCD
3
and a neighboring second transfer gate
10
a
′ in the VCCD region (See
FIG. 2
a
).
A method of fabricating the first, second, third and fourth transfer gates
7
,
10
a
,
10
b
and
13
a
formed between the photodiodes
4
in the row direction is described below. Referring to
FIG. 4
a
, P-type ions are implanted into N-type semiconductor substrate
1
and thermal diffusion is carried out to form P-well
2
to a predetermined depth. A pattern for forming photodiodes
4
is formed on P-well
2
, and N-type impurity ions are implanted into P-well
2
to a predetermined depth to form a plurality of photodiodes
4
in a matrix. Then, a P-type channel stop region
5
is formed in a portion of P-well
2
between photodiodes
4
so as to come into contact with one side of each of photodiodes
4
in the row direction. A first interlevel oxide layer
6
is thinly formed on the overall surface of the substrate
1
, and a first polysilicon layer is formed thereon. The first polysilicon layer is anisotropic-etched to leave polysilicon on the channel stop region
5
between photodiodes
4
and form the first transfer gate
7
.
Referring to
FIG. 4
b
, an oxide layer is deposited through chemical vapor deposition (CVD) and anisotropic-etched to form a block oxide layer
8
on a center portion of the first transfer gate
7
. A second interlevel oxide layer
9
is formed to cover the exposed portions of the first transfer gate
7
, and a second polysilicon layer
10
is formed over the substrate
1
. A photoresist
11
is coated on second polysilicon layer
10
, and then selectively exposed and developed. Referring to
FIG. 4
c
, second polysilicon layer
10
is anisotropic-etched using the patterned photoresist
11
as a mask to form second and third transfer gates
10
a
and
10
b
which are superposed on the edges of first transfer gate
7
and are arranged on neighboring photodiodes
4
in parallel. A third interlevel oxide layer
12
is formed to cover second and third transfer gates
10
a
and
10
b
, and a third polysilicon layer
13
is formed over the substrate
1
. A photoresist
14
is coated on third polysilicon layer
13
, and patterned through exposure and development processes.
Referring to
FIG. 4
d
, the third polysilicon layer
13
is anisotropic-etched using the patterned photoresist as a mask to form the fourth transfer gate
13
a
, which is placed over the first transfer gate
7
in the row direction and is superposed on the second and third transfer gates
10
a
and
10
b
and another second transfer gate
10
a
′ of a neighboring photodiode
4
.
The operation of the above conventional CCD is explained below. As shown in
FIG. 3
, fourth transfer gate
13
a
formed of third polysilicon layer
13
and formed between photodiodes
4
in the row direction, is clocked. Namely, a single readout is applied to fourth transfer gate
13
a
, when the charges accumulated in the photodiode
4
are transferred to the VCCD (i.e., BCCD
3
), to thereby read-out the charges to the VCCD. Then, the charges, which have been moved to the VCCD, are transmitted to the HCCD according to clock timings TG
1
, TG
2
, TG
3
and TG
4
for the first, second, third and fourth transfer gates
7
,
10
a
,
10
b
, and
13
a
. Here, it is difficult to transmit the charges stored in one photodiode
4
to the VCCD completely because the second and third transfer gates
10
a
and
10
b
come into contact with neighboring photodiodes
4
. Thus, only fourth transfer gate
13
a
is clocked when the charges are transmitted from photodiode
4
to the VCCD.
The aforementioned conventional CCD has the following problems. First of all, since the second and third transfer gates, placed between the photodiodes in the row direction are superposed on one side of the first transfer gate, the capacitance between the polysilicon layers increases as their widths widen. The structure of the CCD also makes it difficult to reduce the size of the CCD. Furthermore, only the fourth transfer gate formed of the third polysilicon layer is tri-level clocked when the signal charges are read-out. Accordingly, three-dimensional effects increase as the pixel size is reduced, and this obstructs complete readout.
SUMMARY OF THE INVENTION
A ccordingly, the present invention is at least directed to a CCD and method of fabricating the same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
Another object of the present invention is to provide a CCD and method of fabricating the same, in which the fill factor of its pixel increases to improve the sensitivity, and signal charges are easily and completely read-out at a low electrode voltage.
These and other objects are achieved by a charge coupled device, comprising: a substrate; at least two photodiodes formed in the substrate; a first insulating layer formed on the substrate; a first transfer gate formed on a portion

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