Patent
1983-10-06
1986-05-20
Edlow, Martin H.
357 2314, 357 231, 357 59, 357 41, 357 53, 357 238, H01L 2978
Patent
active
045905061
ABSTRACT:
By the use of high-ohmic polycrystalline silicon (poly) in MIS elements, a depletion layer can be formed in the poly material which brings about an electric decoupling between the poly (gate) and the underlying semiconductor body. This effect can be utilized advantageously in various circuit elements, such as in CCD's, in order to obtain a favorable potential distribution in the substrate; in MOS transistors in order to reduce the parasitic capacities; and in high-voltage devices in order to increase the breakdown voltage at the edge of the field plate (resurf).
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Whelan et al., "Resistive-Insulated-Gate Arrays and Their Applications . . . " Phillips Research Reports, vol. 30, No. 6, Dec. 1975, pp. 436-482.
Hu et al., "A Resistive-Gated IGFET Tetrode," IEEE Trans. on Electron Devices, vol. ED-18, No. 7, Jul. 1971, pp. 418-425.
Biren Steven R.
Edlow Martin H.
Fallick E.
Mayer Robert T.
U.S. Philips Corporation
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