Charge-controlling semiconductor integrated circuit

Details Charge-controlling semiconductor integrated circuit Charge-controlling semiconductor integrated circuit

2009-06-04

2011-10-11

Aurora, Reena (Department: 2858)

Electricity: battery or capacitor charging or discharging

Battery or cell charging

With detection of current or voltage amplitude

C320S157000, C320S158000, C320S159000

Reexamination Certificate

active

08035355

ABSTRACT:
Disclosed is a charge-controlling semiconductor integrated circuit including: a current-controlling MOS transistor; a current detection circuit including a 1/N size current-detecting MOS transistor; and a gate voltage control circuit, wherein the current detection circuit includes an operational amplifier circuit, a bias condition of the current-detecting MOS transistor becomes same as the current-controlling MOS transistor based on an operational amplifier circuit output, voltage drops in lines from drain electrode to a corresponding input point of the operational amplifier circuit become the same by a parasitic resistance, and when the output of the operational amplifier circuit is applied to a control terminal of the bias condition controlling transistor, the drain voltages become the same potential, and the line from the drain electrode of the current-detecting MOS transistor to the input point is formed to be redundantly arranged inside the chip so that a parasitic resistance becomes a predetermined value.

REFERENCES:
patent: 5835361 (1998-11-01), Fitzgerald
patent: 6377381 (2002-04-01), Matsuo
patent: 6407532 (2002-06-01), Ruha
patent: 6507171 (2003-01-01), Ruha et al.
patent: 6605925 (2003-08-01), Tange et al.
patent: 6614205 (2003-09-01), Nakashimo
patent: 7253589 (2007-08-01), Potanin et al.
patent: 7737664 (2010-06-01), Matsunaga
patent: 2002/0158654 (2002-10-01), Graf
patent: 2004/0164786 (2004-08-01), Yamamoto et al.
patent: 2006/0028192 (2006-02-01), Ryu et al.
patent: 2007/0126476 (2007-06-01), Nakashima
patent: 2008/0018387 (2008-01-01), Ryu et al.
patent: 07-113826 (1995-05-01), None
patent: 09-082893 (1997-03-01), None
patent: 2000-284195 (2000-10-01), None
patent: 2002-209340 (2002-07-01), None
patent: 2004-259902 (2004-09-01), None
patent: 2007-134624 (2007-05-01), None
Japanese Office Action dated Apr. 20, 2010 and English translation thereof in counterpart Japanese Application No. 2008-149032.
Taniguchi, Kenji. “CMOS Anarogu Kairo Nyumon (Introduction to CMOS analog Circuit)”. Japan: CQ Publishing Co., Ltd., 2006., 4thedition, pp. 152-155. (and partial English translation thereof).
Extended European Search Report dated Nov. 11, 2009 (5 pages), issued in counterpart European Application No. 09161921.3.

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