Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Slope control of leading or trailing edge of rectangular or...
Reexamination Certificate
2001-12-11
2003-12-09
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Slope control of leading or trailing edge of rectangular or...
C327S538000
Reexamination Certificate
active
06661268
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to an output driver for integrated circuits, and more specifically to an apparatus and method for a bus output driver for integrated circuits.
Integrated circuits connect to and communicate with each other. Typically, integrated circuits communicate with each other using a bus with address, data and control signals.
In
FIG. 1
, a bus
20
interconnects a memory controller
22
and memory modules (RAMS)
24
,
26
,
28
. Physically, the bus comprises the traces on a printed circuit board, wires or cables and connectors. Each of these integrated circuits has a bus output driver circuit
30
that interfaces with the bus
20
to drive data signals onto the bus to send data to other ones of the integrated circuits. In particular, the bus output drivers
30
in the memory controller
22
and RAMS
24
,
26
,
28
are used to transmit data over the bus
20
. The bus
20
operates or transmits signals at a speed that is a function of many factors such as the system clock speed, the bus length, the amount of current that the output drivers can drive, the supply voltages, the spacing and width of the wires or traces making up the bus, the physical layout of the bus itself and the resistance of a pull up resistor attached to each bus.
The address, data and control lines making up the bus will be referred to as channels. In some systems, all channels connect to a pull-up resistor Z
0
. Typically the resistance of the pull up resistor is 28 ohms.
Output drivers for use on a bus, such as is shown in
FIG. 1
, are preferably current mode drivers, which are designed to drive the bus
20
with a determinable amount of current substantially independent of the voltage on the driver output. The output impedance of the driver
30
is a good metric of how much the driver's current will change with voltage changes on the driver's output, a high output impedance being desirable for the current mode driver. In addition, a high output impedance is desirable to minimize transmission line reflections on the bus when a particular driver
30
receives voltage changes from another driver on the bus
20
. In such a case, a driver with a high output impedance will not substantially alter the impedance of the bus
20
, thus causing only a small portion of a wave to be reflected at the location where the driver
30
is attached to the bus.
FIG. 2A
shows a prior art bus output driver circuit
30
which has an output multiplexor
32
that connects to an output current driver
34
at q-node
40
. The q-node
40
refers to the physical connection between the output multiplexor
32
and the output current driver
34
. A q-node signal is output to the q-node
40
. The q-node signal is a voltage level that causes the output current driver
34
to drive a corresponding voltage level on the bus
20
(also herein called a bus channel).
The output multiplexor
32
receives a clock signal at a clock input
42
, and receives odd and even data signals at the odd data and even data inputs
44
and
46
, respectively. The odd and even data signals are synchronized to the clock signal. The output multiplexor
32
transmits the data from the odd data and even data inputs onto the q-node
40
on the rising and falling edges of the clock signal, respectively.
The slew rate and output current of the bus output driver
30
are controllable. A set of slew rate control bits
50
is used to select the slew rate of the transitions of the q-node signal. A slew rate estimator
48
may be used to generate the slew rate control bits
50
. Alternately, the slew rate control bits
50
may be generated by a process detector, a register that is programmed with a fixed value during manufacture or during testing of the device after manufacture, or by any other type of slew rate detection circuitry. The source of the slew rate control bits
50
may be external to the bus output driver
30
. The output current driver
34
outputs a signal, called Vout, that corresponds to the q-node signal, onto the bus channel
20
. A current control block
52
outputs a set of current control bits
54
that select the amount of current used to drive data onto the bus channel
20
. The current control block
52
may be external to the bus output driver
30
, and may be implemented as a current level detector or as a register programmed with a fixed value during or after manufacture of the device.
FIG. 2B
is a schematic of the prior art output multiplexor and output current driver of FIG.
2
A. The clock, odd data and even data signals are input to multiple current control blocks
62
,
64
and each current control block
62
,
64
outputs a q-node signal on a q-node
66
,
68
,
70
,
72
. In
FIG. 2B
, the q-nodes
66
,
68
,
70
,
72
are also designated as q<
6
>-q<
0
>, respectively. When the q-node signal has a sufficiently high voltage level, a corresponding transistor T
0
-T
6
in the output current driver becomes active and pulls Vout low. Each q-node signal drives a binary weighted pulldown device T
0
-T
6
in the output current driver. In other words, multiple q-nodes
66
,
68
,
70
,
72
are used to drive a single channel
20
of the bus. The transistors T
0
-T
6
are n-type metal-oxide-semiconductor (MOS) transistors and are binary weighted with respect to each other. In particular, each transistor T
0
-T
6
will drive or sink a predetermined amount of current with respect to I
out
. Transistor T
0
sinks 2
0
or 1×I
out
(e.g., about 0.26 milliamps minimum), transistor T
4
sinks 2
4
or 16×I
out
, transistor T
5
sinks 32×I
out
, and transistor T
6
sinks 64×I
out
.
Since the current control blocks
62
,
64
are similar, one current control block
62
will be described. The current control block
62
has an input block
82
and a pre-driver
84
. The input block
82
is responsive to a current control signal output on a current control bit line
84
. In
FIG. 2B
, the current control signals are shown as Current Control <
0
> through Current Control <
6
>. Each q-node
66
,
68
,
70
,
72
is associated with a separate current control signal. The current control signal enables the NAND gates
86
,
88
to respond to the odd and even data signals. Each NAND gate
86
,
88
outputs its signal to a pair of passgates
92
,
94
, respectively. The passgate pairs
92
,
24
are responsive to the clock signal such that one passgate pair
92
,
94
is on at a time, outputting either the odd data or even data signal. The output of the passgates
92
,
94
is connected to the pre-driver
84
.
If the current control signal on the current control bit line
84
is at a low voltage, the NAND gates
86
,
88
output a high voltage level regardless of the voltage level of the odd or even data signal, thereby causing a “low” voltage level at the associated q-node and disabling the corresponding transistor in the output current driver.
If the current control signal on the current control bit line
84
is at a high voltage level, the NAND gates
86
,
88
are enabled, and the predriver
84
, q-node and output current driver are responsive to the odd and even data signals.
In the prior art output driver
30
, the output impedance of the output driver
30
is not well controlled, and is determined by the value of a supply voltage, Vcc (the high voltage for the q-node), the output voltage when it is being driven low, and the characteristics of the transistors in the output current driver
34
.
FIG. 2C
is a schematic of the prior art pre-driver
84
of FIG.
2
B. The predriver has many predriver sub-blocks
96
,
98
,
100
. Each predriver sub-block
96
,
98
,
100
has an inverter
11
,
12
,
13
and a passgate pair
102
,
104
,
106
respectively. One predriver sub-block
96
is always enabled with the gate of each transistor of the passgate pair
102
connected to the power supply Vcc and to ground, respectively. The other passgate pairs
104
,
106
of the predriver sub-blocks
98
,
100
connect to the slew rate control bits, Slew
Ching Michael Tak-Kei
Kim Jun
Knorpp Kurt T.
Kushiyama Natsuki
Stark Donald C.
Cunningham Terry D.
Pennie & Edmonds LLP
Rambus Inc.
Tra Quan
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