Charge-based miller coefficient computation

Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation

Reexamination Certificate

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C716S113000

Reexamination Certificate

active

08078447

ABSTRACT:
A method of estimating a Miller coefficient for an aggressor network and a victim network coupled by a coupling capacitor includes synthesizing a reduced order system from the aggressor network and the victim network, estimating an active area across the coupling capacitor for an aggressor induced noise signal based on the reduced order system, calculating an estimate of the Miller coefficient based on the active area of the aggressor induced noise signal, and outputting the calculated estimate of the Miller coefficient.

REFERENCES:
patent: 6665845 (2003-12-01), Aingaran et al.
patent: 7739640 (2010-06-01), Abbaspour et al.
patent: 2004/0034840 (2004-02-01), Chen
patent: 2006/0059446 (2006-03-01), Chen et al.
Chen et al. “Miller Factor for Gate-Level Coupling Delay Calculation”, IEEE 2000., p. 68-74.
Chen et al. “Closed-Form Crosstalk Noise Delay Metrics”. Analog Integrated Circuits and Signal Processing., 2003, p. 143-156.
Mayergoyz et al. “Basic Electric Circuit Theory”., Academic Press., 1997, p. 107-110.
Kulkarni et al. “A sensitivity-Based Approach to Analyzing Signal Delay Uncertainty of coupled Interconnects”., IEEE. Sep. 2005., p. 1336-1346.

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