Charge balancing method in a current input ADC

Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion

Reexamination Certificate

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C341S155000

Reexamination Certificate

active

07372392

ABSTRACT:
A method for charge balancing in a current input ADC including maintaining a low capacitance value at the integrator output node where the capacitance value is independent of the integrator output voltage and operating conditions, generating a first voltage pedestal at a first active device switch at the end of the autozero phase having a first voltage polarity and a first magnitude, generating a second voltage pedestal at a second active device switch at the end of the integration phase having an opposite voltage polarity and the first magnitude, and summing the first voltage pedestal with the second voltage pedestal. The difference between the first voltage pedestal and the second voltage pedestal results in a net voltage error. The first and second voltage pedestals have the first magnitude under all operating conditions of the modulator and the two voltage pedestals cancel to yield a small net voltage error.

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