Charge and discharge control circuit and apparatus for...

Electricity: battery or capacitor charging or discharging – Battery or cell discharging – With charging

Reexamination Certificate

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Details

C370S902000

Reexamination Certificate

active

06194871

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a charge and discharge control circuit and an apparatus for preventing overcharge and overdischarge in a secondary battery pack such as a lithium-ion secondary battery used in various types of portable equipment. The present invention particularly relates to a charge and discharge control circuit and an apparatus which are optimum in view of battery life and ensuring the safety of a battery.
2. Prior Art
Secondary batteries such as a lithium-ion secondary battery are frequently used following the spread of various types of portable equipment. Because of its structure and chemical property, however, a secondary battery has the following disadvantages. In an overcharge state, gas due to solution vaporization may be generated and solution leakage may occur within a battery. In an overdischarge state, electrodes may be eluted within a solution. As a result, there is a possibility of the breakdown of the battery, the deterioration of battery characteristics and the like. Therefore, measures have been conventionally taken against overcharge and overdischarge in various manners.
FIG. 7
is an internal circuit diagram showing secondary battery packs
200
and
208
used for a battery such as a conventionally used lithium-ion secondary battery. In this case, the secondary battery packs are used as power supplies for a notebook-size personal computer (to be referred to as “notebook PC” hereinafter). The two battery packs
200
and
208
are connected to the internal circuit
205
of the notebook PC through back flow prevention diodes D
1
and D
2
.
In the battery pack
200
, a plurality of secondary battery cells (which are three secondary battery cells
202
H,
202
M and
202
L in
FIG. 7
) are connected in series to thereby constitute a battery
202
as a whole. The negative voltage side of the battery
202
is connected to the negative terminal Batt− of the battery pack
200
and the source terminal of a discharge control P type field effect transistor (to be referred to as “FET” hereinafter)
203
is connected to the positive voltage side of the battery
202
. Also, the drain terminal of the FET
203
is connected to the drain terminal of a charge control P type FET
204
and the source terminal of the FET
204
is connected to the positive terminal Batt+ of the battery pack
200
. Battery voltage is thus outputted between the negative terminal Batt− and the positive terminal Batt+ of the battery pack
200
and then supplied to the internal circuit
205
of the notebook PC acting as a load. A charger detection terminal OCV is connected to the positive terminal Batt+ of the battery pack
200
to detect that a charger (not shown) is connected to the battery pack. In addition, a current limiting resistor R
201
is inserted between the positive terminal Batt+ and the OCV terminal to prevent overcurrent at the time of erroneously connecting the battery pack
200
and the charger (not shown).
In the charge and discharge control circuit
201
, a voltage detector circuit
220
is connected to each of the battery cells
202
H,
202
M and
202
L and monitors the voltage value of each of the battery cells
202
H,
202
M and
202
L. Each battery cell
202
H,
202
M or
202
L has a structure independent of other cells due to the need to protect the cell against overcharge and overdischarge independently. If at least one of the battery cells
202
H,
202
M and
202
L is turned into an overcharge state, then the output of the corresponding voltage detector circuit
220
is inverted and the gate terminal COUT of the charge control P type FET
204
is set at a high level by an overcharge control circuit
231
outputting a logic sum of the voltage detector circuits
220
to thereby make the FET
204
nonconductive and disconnect a charge path.
Conversely, if at least one of the battery cells
202
H,
202
M and
202
L is turned into an overdischarge state, then the output of the corresponding voltage detector circuit
220
is inverted and the gate terminal DOUT of a discharge control P type FET
203
is set at a high level by an overdischarge control circuit
232
outputting the logical sum of the voltage detector circuits
220
to thereby make the FET
203
nonconductive and disconnect a discharge path. At the same time, this overdischarge state is latched by a latch circuit
240
and the charge and overdischarge control circuit
201
is turned into a standby state. At this moment, if the overcharge state is not detected, a bias circuit
250
is made inactive and the internal bias of the charge and discharge control circuit
201
is stopped to turn the circuit
201
into a complete dormant state. Then, no current is consumed in the charge and discharge control circuit
201
, so that the secondary battery
202
which has supplied the internal bias is not consumed and the battery voltage is not decayed for a long time. Accordingly, it is unlikely that after the circuit
201
is halted in an overdischarge state, the battery voltage is unnecessarily decayed and battery characteristics unnecessarily deteriorates.
In recharge operation, the negative terminal and the positive terminal of the charger (not shown) are connected to the negative terminal Batt− and the positive terminal Batt+ of the battery pack, respectively, thereby turning the charger detection terminal OCV into a high level. Thus, the latch circuit
240
which has latched the overdischarge state is reset, the charge and discharge control circuit
201
is out of the standby state, the bias circuit
250
starts operation and the internal bias is applied. The gate terminal COUT of the charge control P type FET
204
is turned into a low level by the overcharge control circuit
231
, the FET
204
is made conductive and thereby charge operation is started. This state continues until an overdischarge state is detected and the battery cells
202
H,
202
M and
202
L are charged in this state until then.
Next, it is assumed that the battery pack
200
is in an overdischarge state and the other battery pack
208
is in a charge state. In this case, while the voltage of the positive terminal Batt+ of the battery pack
200
is low in level, the cathode of the diode D
1
, i.e., the cathode of the diode D
2
is high voltage level and the diode D
2
is reversely biased and a reverse leak current flows into the battery pack
200
. If the voltage level of the charger detection terminal OCV is increased due to the leak current, there is fear that the charge and discharge control circuit
201
erroneously recognizes that the charger (not shown) is connected to the battery pack
200
and turns on the internal bias, and that charge operation is erroneously started. In this example, to prevent this erroneous operation, a leak current drawing N-type FET (M
1
) is connected between the charger detection terminal OCV and a reference voltage, and made conductive in a standby state to thereby let the leak current flow to the reference potential. By regulating the residual voltage of the charger detection terminal OCV to about 0.3V with respect to the leak current of about 300 &mgr;A while the leak current drawing N-type FET (M
1
) is conductive, the charge operation by the latch reset is prevented from being erroneously started.
In the above-stated charge and discharge circuit
201
, after the battery pack
200
is turned into an overdischarge state, the internal bias turns into a halt state under conditions that all of the battery cells
202
H,
202
M and
202
L are not in an overcharge state, the consumption of the battery
202
is stopped and thereby the battery voltage is not decayed for a long time.
Nevertheless, there exists a leak current, though only slightly, in the battery
202
itself or the charge and discharge control circuit
202
or the like. Then, if the battery
202
is left untouched for a long time, the battery voltage gradually decays and the battery is completely discharged without any residual voltage in the end

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