Characterizing the integrity of interconnects

Details Characterizing the integrity of interconnects Characterizing the integrity of interconnects

2008-07-01

2008-07-01

Coleman, W. David (Department: 2823)

Semiconductor device manufacturing: process

With measuring or testing

C324S094000, C324S519000, C257SE21521

Reexamination Certificate

active

07393702

ABSTRACT:
The present invention provides for a system and method of characterizing the integrity of a barrier structure. The barrier structure is an interconnect comprising a porous dielectric layer sandwiched between at least one barrier layer and at least one conducting layer. The method of characterizing the integrity of such an interconnect includes providing an interconnect, infiltrating the interconnect with a solution comprising electrolytes, applying an external bias to the infiltrated interconnect, and characterizing the integrity of the interconnect after application of the external bias.

REFERENCES:
patent: 6368887 (2002-04-01), Lowrey et al.
patent: 6900652 (2005-05-01), Mazur
patent: 7001785 (2006-02-01), Chen

Affiliated with

Also associated with

Rating

Characterizing the integrity of interconnects does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Characterizing the integrity of interconnects, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Characterizing the integrity of interconnects will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2806854