Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2000-06-01
2002-02-12
Nguyen, Vinh P. (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S1540PB, C324S765010, C324S762010, C324S762010
Reexamination Certificate
active
06346820
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a characteristics evaluation circuit incorporated into a semiconductor wafer and its evaluation method.
2. Description of the Related Art
In a process for manufacturing a semiconductor wafer, characteristics of semiconductor chips are measured at each step. For example, threshold voltage characteristics of MOS transistors, resistance characteristics of conductive layers, capacitance characteristics of conductive layers and the like are measured to check the manufacturing steps.
In order to measure the above-mentioned characteristics of the semiconductor chips, a characteristics evaluation circuit is incorporated into each of the semiconductor chips, a scribe area between the semiconductor chips or a characteristics evaluation area having the same size as the semiconductor chips.
A prior art characteristics evaluation circuit is constructed by a dummy element associated with at least two pads. This will be explained later in detail.
After the characterisctics of the characteristics evaluation circuit are measured, the characteristics evaluation circuit become unneccessary. If the semiconductor chips or the semiconductor wafer associated with such a characteristics evaluation circuit is shipped, any third party can easily analyse the characteristics of the semiconductor chips by placing probes on the pads of the characteristics evaluation circuit.
In order to destroy or inactivate the characteristics evaluation circuit, a first approach is that fuses are connected to the pads of the dummy element. After the characteristics of the characteristics evaluation circuit are measured, the fuses are melted down by a laser trimming process or the like. This also will be explained later in detail.
In the above-mentioned first approach, however, it is impossible to accurately measure the dummy element due to the presence of resistances by the fuses.
A second approach is to directly destroy the dummy element by applying laser or mechanical stress thereto. This also will be explained later in detail.
In the second approach, however, since the dummy element has various types with different sizes, it is impossible to effectively destroy the dummy element, which also increases the manufacturing cost.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a characteristics evaluation circuit for a semiconductor wafer, capable of being easily destroyed or inactivated.
Another object is to provide an improved characteristics evaluation method for a semiconductor wafer.
According to the present invention, in a characteristics evaluation circuit incorporated into a semiconductor wafer, a dummy element is connected to at least two pads, and a depletion type MOS transistor is connected between the pads. A fuse is connected to a gate of the depletion type MOS transistor, and a gate voltage control pad is connected to the fuse.
When evaluating the characteristics of the dummy element, an appropriate voltage is applied to the gate voltage control pad so as to turn OFF the depletion type MOS transistor. Then, probes are placed on the pads to measure characteristics of the dummy element. Finally, the fuse is cut.
Note that, when the fuse is cut, the gate of the depletion type MOS transistor is in a floating state. In this state, since the pad is not connected to the gate of the depletion type MOS transistor, the gate of the depletion type MOS transistor is very small. Therefore, since only a small charge is injected into the floating state gate, the gate voltage of the depletion type MOS transistor remains at zero (ground), so that the depletion type MOS transistor is always in an ON state.
REFERENCES:
patent: 5034687 (1991-07-01), Huang
patent: 5896040 (1999-04-01), Brannigan
patent: 5994915 (1999-11-01), Farnworth
patent: 6225818 (2001-05-01), Park
patent: 6-295948 (1994-10-01), None
Hutchins, Wheeler & Dittmar
Nguyen Trung
Nguyen Vinh P.
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