Characteristically terminated write driver with compensation...

Details Characteristically terminated write driver with compensation... Characteristically terminated write driver with compensation...

2001-03-06

2003-12-30

Faber, Alan T. (Department: 2651)

Dynamic magnetic information storage or retrieval

General processing of a digital signal

Head amplifier circuit

C360S068000, C360S061000, C327S110000

Reexamination Certificate

active

06671113

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a technique of using an inductive recording head to store information onto a magnetic medium, and in particular to circuits for reducing the current reversal time of the current through the inductive recording head for write drivers having an H-type configuration.
2. Description of the Related Art
Typically, a conventional H-type current write driver drives a magnetic recording head via a suspension interconnect. Because of the relatively low data rates, the current reversal times in the magnetic recording head are relatively large with respect to the echo-return time (e.g., twice the “time of flight” of the interconnect) which, for an industry standard interconnect in a 3.5 inch drive has a length of 5 cm, is approximately 500 picoseconds. As a result, when the next current reversal arrives at the head, the echoes of the previous current reversal have dissipated enough not to cause a noticeable transition shift in the written data.
However, the ever increasing data rates require the current reversal time to be much smaller now to allow for the lower minimum time interval T between two adjacent current reversals commensurate with the higher data rate (e.g., T=1/DR, where DR is data rate in bits/sec). This minimum time interval is a so-called “bit cell time window”. With these higher data rates, T is becoming so small that the echoes of a previous current reversal may not have dissipated enough at the next current reversal, thereby causing a timing shift in the written data (timing distortion).
The conventional write configuration is illustrated in FIG.
1
(
a
), and includes a write driver
10
, an interconnect
12
typically of the integrated lead suspension (ILS) type and having characteristic impedance Z
O
, and a magnetic recording head
14
having write current I
W
and equivalent inductive element L
h
and resistive element R
h
. A cross section of the ILS type of interconnect is illustrated in FIG.
1
(
b
).
The write driver
10
is configured in an “H” topology with the write head
14
at the cross-bar of the “H”. When a data pulse is of one polarity the pair of switches S are closed to permit current flow in one direction in the write head. An opposite polarity data pulse causes switches S_bar to close to permit current flow in the opposite direction in the write head.
As illustrated in the cross-sectional view of FIG.
1
(
b
), the ILS structure typically includes a stainless steel suspension
12
a
, and traces
12
b
,
12
b
′ separated by dielectric
12
c
, typically polymide with a typical dielectric coefficient ∈
r
≈2.7. Traces
12
b
,
12
b
′ have a typical separation of 50 &mgr;m and line width perhaps slightly larger. The signal power travels predominantly between trace
12
b
and the stainless steel suspension
12
a
and between trace
12
b
′ and the suspension
12
a
. The signal power transfer by the transmission path formed by the
12
b
and
12
b
′ trace can be neglected. Therefore, the two transmission lines in FIG.
1
(
a
) (each with a single-ended characteristic impedance Z
0
/2, half the differential characteristic impedance Z
0
of the ILS) are an adequate representation of the ILS.
In the conventional systems, it is also known to source-terminate the ILS with an impedance substantially equal to the characteristic impedance of the ILS in order to absorb the reflections coming from the write head Because these reflections are no longer reflected back to the write head, they do not upset the timing of subsequent current reversals in the write head. FIG.
2
(
a
) shows a conventional source-terminated current write driver including impedance matching resistors
20
. FIG.
2
(
b
) shows a conventional source-terminated voltage write driver.
The disadvantage of this conventional characteristic source termination scheme is that the achievable write head current reversal time is now determined by the inductance of the write head and the characteristic impedance of the ILS:
t
10,90%
=2.2
L
h
/(
Z
O
+R
h
),
where t
10,90%
is the reversal time interval from 10% to 90% of the steady state signal levels. L
h
is the head inductance; and R
h
is the head resistance.
As a result, using the rule of thumb that the bit cell time window T must be equal or larger than 2·t
10,90%
, the maximum achievable data rate is given by:
Data Rate
max
=(
Z
O
+R
h
)/4.4
L
h
[bits/sec]
With L
h
=40 nH, R
h
=15 &OHgr; and Z
O
=70 &OHgr;, a maximum data rate is found of 480 Mbits/sec, or 60 Mbytes/sec.
To improve on this data rate, the characteristic impedance of the ILS could be made higher and/or the inductance of the head could be reduced. However, increasing the characteristic impedance of the ILS is difficult because the width of the traces becomes disappearingly small (for acceptable tolerances in the characteristic impedance of these lines about 80 &OHgr; seems to be the maximum achievable impedance given the materials and dimensions used) Lowering the head inductance without increasing the write current to excessive levels has shown to be difficult. Such excessive write currents would require large area transistors in the write driver, associated with larger parasitics. This would slow down the write driver.
SUMMARY OF THE INVENTION
In view of the foregoing and other problems, it is, therefore, an object of the present invention to provide a structure and method for improving the write speed of an inductive recording head.
It is another object of the invention to achieve the shortest possible time interval between two write current reversals in an inductive recording head, as determined to be the current reversal time of the magnetic write head.
It is yet another object of the invention to achieve this shortened time interval by eliminating transition shift (e.g., timing distortion) in the written data caused by the reflections traveling along the interconnect between the write head and the write driver.
It is another object of the invention to achieve this shortened time interval by overcoming the limitation placed on the current reversal time by a relatively large ratio of head inductance and characteristic impedance of the interconnect by temporarily enlarging the source strength of the write driver immediately following each current reversal.
It is still another object of the invention to achieve the write driver source strength enlargement using a spiking circuit based on a current mirror circuit.
It is another object of the invention to reduce the write current reversal time by compensating for skin-effect losses in an Integrated Lead Suspension (ILS) type of interconnect between the write driver and the write head.
It is yet another object of the invention to achieve this skin-effect compensation by increasing the resistance value of the termination resistors used for suppressing echoes returning from the magnetic write head above the theoretical value.
In a first aspect of the present invention, a magnetic recording circuit is disclosed, having a magnetic write head receiving an input write signal having a first amplitude, and an enhancement circuit increasing a signal strength at the input of the magnetic write head above that first amplitude for a predetermined time interval immediately after every polarity reversal, where the predetermined time interval representing a transition period of the magnetic write head, defined as a time period for a current through the magnetic write head to reach a substantially steady state value following a polarity reversal
In a second aspect of the present invention, a magnetic recording circuit is disclosed having a magnetic write head receiving an input write signal having a first amplitude, a write driver output stage providing the write signal as an output, the write driver output stage including a source-side termination circuit having output impedance Z
S
, and an interconnect circuit having an input, an output, and a characteristic imped

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