Data processing: structural design – modeling – simulation – and em – Modeling by mathematical expression
Reexamination Certificate
1999-03-12
2001-12-11
Teska, Kevin J. (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Modeling by mathematical expression
Reexamination Certificate
active
06330526
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a characteristic variation evaluation method for generating a worst-case parameter to evaluate characteristic variations of semiconductor devices; a characteristic variation evaluation unit; and a recording medium for storing a characteristic variation evaluation program, all of semiconductor devices.
2. Description of the Background Art
Fluctuations in semiconductor process conditions stochastically cause circuit performance variations. Such variations have been relatively widened with the shrinking of minimum device size, so that it is getting necessary to estimate performance variations, along with standard performance, in the device development phase.
For instance, there are a method for detecting independent model parameters by a factor analysis or a principal component analysis in order to represent variations of every parameter by the model parameters; and a method for classifying parameters into groups with consideration for their correlation and analyzing sensitivity of each classified group to circuit performance in order to represent circuit performance variations by the sensitivity and the parameter variations.
These methods are both intended to represent variations of characteristic values by the parameter variations, but the use of simulations therein costs much labor. Hence, Technical Report SDM96-122 (1996-11) of the Institute of Electronics, Information and Communication Engineers, for example, provides a method for representing performance variations of basic circuits due to fluctuations in process conditions by circuit model parameters which are obtained by a principal component analysis and a multiple regression analysis, and determining parameters having the highest probability of being the worst case under a certain condition of circuit performance, as parameters representing the worst case (this method is hereinafter referred to as “basic method.”)
The features of this conventional basic method are as follows:
(1) To determine parameter values corresponding to the worst case with consideration for a correlation between parameters;
(2) To increase accuracy in probability estimation as compared with a method using corner models;
(3) To determine parameter values by specifying values corresponding to the worst case of circuit performance; and
(4) To reduce the required number of simulations for parameter verification.
Outline of Basic Method
A general flow of the basic method is shown in FIG.
13
. First, performance (drain current, circuit delay etc.) of a large number of chips is measured, and a small number of principal parameters (effective channel length, threshold voltage etc.) of model parameters in circuit simulation are extracted from a plurality of chips (step ST
1
). After eliminating outliers (step ST
2
), each parameter is applied to distribution (step ST
3
). Then, a typical chip (typical semiconductor device) giving a standard performance is selected (step ST
4
) and its principal parameters are extracted as typical parameters (step ST
5
). At the same time, parameters necessary to represent variations of a characteristic value in the worst case are selected by a partial regression analysis (step ST
6
) and a multiple regression analysis (step ST
7
). By adapting the basic method to those selected parameters, a parameter value corresponding to the worst case (worst-case parameter) is determined (step ST
8
). Finally, the parameters representing the variations of the characteristic value, out of the typical parameters extracted from the typical chip, are replaced by the worst-case parameter to conduct simulation and verification of the worst-case parameter (step ST
9
).
We will give a further detailed description of each step on the flow chart in FIG.
13
. First, parameter extraction at step ST
1
is described. The parameters to be extracted at step ST
1
are, for example, effective channel length Leff; effective channel width Weff; external resistance RSH; oxide film thickness Tox; threshold voltage Vth; junction capacitance of plane components Cj; and junction capacitance of line components Cjsw. Of the model parameters in circuit simulation, the above parameters are considered as principal parameters having physical connotations and influence on circuit performance such as circuit delay Tpd and drain current Idmax.
Next, outlier elimination at step ST
2
is described. At step ST
2
, parameter sets of chips at least having one outlier are eliminated from the principal parameters in circuit simulation extracted from a plurality of chips. Under present circumstances, there are a method for converting data of each parameter including outliers into an independent variable by a principal component analysis and eliminating outliers until no correlation is found in data of converted variables; and a method for eliminating outliers by referring to conversion and distribution of each parameter.
The former method by the principal component analysis is, for example, shown in
FIGS. 14 and 15
. The vertical axis denotes a second principal component and the horizontal axis denotes a first principal component. In
FIG. 14
, those principal components are correlated because of outliers mixed therein. By eliminating the outliers, a distribution of plots is rounded as shown in
FIG. 15
, in which the principal components are uncorrected. Such operation is performed on certain principal components for each parameter to eliminate outliers.
Next, application to distribution at step ST
3
is described. At step ST
3
, characteristic values and parameters are applied to suitable probability distribution. Assuming in general that a random variable influenced by various non-specific factors approximately has a normal distribution, a characteristic value is applied to normal distribution and parameters are applied to multivariate normal distribution.
FIG. 16
shows a characteristic value and principal parameters applied to normal distribution. As shown, the parameters and the characteristic value almost have a normal distribution, and there is a correlation between the parameters as shown in FIG.
17
.
Next, chip selection for typical parameter selection at step ST
4
is described. First, alternatives are narrowed down to chips whose characteristic values are about average in distribution. As necessary, the principal parameters may also be used to narrow down the alternatives. Then, a chip whose principal model parameters have the highest probability density is selected as a typical chip from which all model parameters with typical values in circuit simulation are extracted. At step ST
5
, predetermined parameters (Leff, Vth etc.) of the typical chip (semiconductor device) are extracted as typical parameters.
Next, parameter selection by the partial regression analysis at step ST
6
is described. At step ST
6
, it is checked whether one certain parameter which is considered to contribute to the variations of the characteristic value includes a component other than the components representing the characteristic value. That is, the partial regression analysis reveals a contribution of a certain parameter to the characteristic values.
Next, multiple regression analysis at step ST
7
is described by which a contribution of a parameter set to the characteristic value is confirmed. At step ST
7
, the degree of correlation between measured values and values of linear regression equations calculated from the parameter set selected by the partial regression analysis, is checked. This analysis confirms to what degree the selected parameters can represent the variations of the characteristic value.
Next, a method for determining the worst-case MOSFET model parameter at step ST
8
is described. A variable characteristic value p (circuit delay time, current driving capability etc.) is considered as a random variable having a certain probability distribution. Using a model parameter x in circuit simulation having a large contribution to variations of the characteristic value p, the variations
Jones Hugh
Mitsubishi Denki & Kabushiki Kaisha
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Teska Kevin J.
LandOfFree
Characteristic variation evaluation method of semiconductor... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Characteristic variation evaluation method of semiconductor..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Characteristic variation evaluation method of semiconductor... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2596307