Wave transmission lines and networks – Coupling networks – With impedance matching
Reexamination Certificate
2001-08-17
2004-07-06
Pascal, Robert (Department: 2817)
Wave transmission lines and networks
Coupling networks
With impedance matching
C333S246000, C257S692000
Reexamination Certificate
active
06759921
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to integrated circuit packaging and, more specifically, to a characteristic impedance equalizer and an integrated circuit package employing the same.
BACKGROUND OF THE INVENTION
Reliable operation of electronic devices, especially semiconductor devices, is of a primary importance today. Often the success of a company may depend on the success at which new technology is reliably established, especially in a developing market. Particularly challenging is the general market demand for devices that perform more functions at increasingly faster operating speeds. This demand for increased functionality usually drives the device design toward more complexity, which typically involves higher component densities. Higher densities alone complicate the environment for signal transmissions within the device. The demand for faster signal speeds further exacerbates this condition causing the environments and associated designs that were acceptable at slower signal speeds to cross into the realm of unacceptability.
Signal environments that exist in a semiconductor die may require special attention to insure that the ever closer proximity of signals will not generate cross-talk or other interference conditions. Although challenging, these on-chip detrimental conditions may be overcome through appropriate layout and shielding designs. High speed, high density packaging substrate design, however, typically involves a constant trade-off between cost and electrical signal integrity requirements. To reduce costs, signals are often routed in a microstrip construction where the signal only references one power or ground plane.
Additionally, the construction of a flip chip package, for example, employs a copper stiffener to reduce warpage and a copper heatsink or slug to dissipate heat from the back of the semiconductor die. When a four-layer flip chip packaging substrate is used in this assembly configuration, the traces routed on the top layer are subject to several discontinuities in the electrical environment. One source of discontinuity is the microstrip trace routing from the central cavity area formed under the heatsink and the region under the stiffener. These discontinuities lead to a variation in the characteristic impedance associated with the microstrip traces. This causes reflected noise and losses during signal transmission.
The discontinuity could be eliminated by using a strip line construction wherein the signal is sandwiched between power and ground planes for its entire length. However, this would need additional layers in the packaging substrate thereby increasing the cost. Another approach is to shrink the stiffener opening to bring it closer to an edge of the semiconductor die thereby providing a more uniform and controlled electrical environment for the microstrip traces on the top layer of the packaging substrate. However, this means different stiffener openings for every semiconductor die size. The resultant non-standardization in stiffener opening complicates the overall assembly process and thereby also increase assembly costs.
Accordingly, what is needed in the art is a way to provide a more controlled characteristic impedance that is both robust and cost effective in an integrated circuit package.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, the present invention provides a characteristic impedance equalizer for use with an integrated circuit package having first and second signal transmission zones. In one embodiment, the characteristic impedance equalizer includes a first conductor having a first width and providing a characteristic impedance within the first signal transmission zone. The characteristic impedance equalizer also includes a second conductor, coupled to the first conductor, having a second width and providing substantially the same characteristic impedance within the second signal transmission zone.
In another aspect, the present invention provides a method of manufacturing an integrated circuit package. The method of manufacturing includes providing a substrate configured to be partitioned into first and second signal transmission zones. The method further includes forming a first conductor having a first width and providing a characteristic impedance within the first signal transmission zone and forming a second conductor having a second width and providing substantially the same characteristic impedance within the second signal transmission zone.
In yet another aspect, the present invention provides an integrated circuit package that includes a substrate configured to be partitioned into first and second signal transmission zones. The integrated circuit package also includes a characteristic impedance equalizer with a first conductor having a first width providing a characteristic impedance within the first signal transmission zone and a second conductor having a second width providing substantially the same characteristic impedance within the second signal transmission zone.
The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
REFERENCES:
patent: 5184095 (1993-02-01), Hanz et al.
patent: 6154103 (2000-11-01), Scharen et al.
patent: 6424027 (2002-07-01), Lamson et al.
patent: 6459049 (2002-10-01), Miller et al.
patent: 6518663 (2003-02-01), James et al.
Govind Anand
Ranade Yogendra
Hitt Gaines P.C.
Jones Stephen E.
LSI Logic Corporation
Pascal Robert
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