Characteristic extraction device, characteristic evaluation...

Details Characteristic extraction device, characteristic evaluation... Characteristic extraction device, characteristic evaluation...

2000-01-20

2004-05-11

Teska, Kevin J. (Department: 2123)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Circuit simulation

C703S013000, C703S002000, C324S762010

Reexamination Certificate

active

06735558

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a characteristic extraction technique, a characteristic evaluation technique, a recording medium and a semiconductor device.
2. Description of the Background Art
In the process of developing a logic device, circuit simulation is widely employed for estimating the optimum margins on circuit characteristics.
FIG. 31
is an explanatory diagram showing the outline of circuit simulation. A device referred to as a circuit simulator is employed for executing the circuit simulation. Data related to the characteristics of each element forming the circuit (device) to be simulated and data (referred to as “circuit connection information”) related to connection conditions for each element are input in the circuit simulator. The circuit simulator executes simulation on the basis of the input data, and outputs data related to the characteristics of the circuit. On the basis of the output data, an operator can determine whether or not the circuit operates with the optimum margins and feed back the results of the determination to development of the device.
In development of the state-of-the-art logic device, circuit simulation based on the well-known SPICE model forming the world standard is generally employed in particular. Further, modeling not only employing typical values as the characteristics of the element but also adopting dispersion of the characteristics of the element from the best to the worst values in consideration of errors (process errors) occurring in the process of manufacturing the device, i.e., worst/best modeling is performed. In the worst/best modeling employing SPICE, a method based on E-T (electrical test) data forms the main stream.
In this method, a group of parameters referred to as E-T data are input as the data related to the characteristics of the element. Circuit simulation is executed after the input E-T data are converted to a group of parameters referred to as SPICE parameters necessary for executing simulation based on the SPICE model. The E-T data, which are parameters associable with the SPICE parameters and having physical meanings, can advantageously be directly extracted from the electric characteristics of the element in a short time.
If the element is a MOSFET (MOS field-effect transistor), a threshold voltage Vth, channel shortening DL, external resistance Rds, channel narrowing DW, mobility &mgr; and a saturation velocity Vsat (or a parameter expressing a velocity saturation effect in place of Vsat) are extracted as the E-T data.
FIG. 32
is a sectional view of a MOSFET for illustrating the physical meanings of these parameters. The channel shortening DL is defined as the difference between a channel length (mask length) Lm as the dimension of a mask and an electrically effective channel length (effective channel length) Leff. That is,
DL=Lm−Leff
  (e1)
While not shown in
FIG. 32
, the channel narrowing DW is similarly defined as the difference between a channel width (mask width) Wm as the dimension of the mask and an electrically effective channel width (effective channel width) Weff. That is,
DW=Wm−Weff
  (e2)
Total resistance between a source electrode SS and a drain electrode DD is given by the sum of resistance (channel resistance) Rch of a channel region Ch and the external resistance Rds. Both of the source electrode SS and the drain electrode DD include electrode wires. The external resistance Rds is a resistance component outside the channel region Ch, and generally includes resistance (source/drain resistance) of a source region S and a drain region D and resistance of the electrodes (including the electrode wires). Assuming that Rtot represents the total resistance,
Rtot=Rch+Rds
  (e3)
The external resistance Rds is not important in an element having a large channel length due to large channel resistance Rch. In a refined element, however, the external resistance Rds is important due to small channel resistance Rch. In particular, resistance components of electrodes are unignorable. A gate insulator film OX having a thickness Tox is interposed between a gate electrode and a semiconductor layer.
However, a method of extracting these parameters related to the MOSFET in a mutually matching form has not been known in general. A highly precise extraction method has been devised as to the channel shortening DL and the external resistance Rds as described in Japanese Patent Application No. 10-213019 (1998) (hereinafter referred to as literature 1), for example, and a method of precisely extracting the channel narrowing DW has been devised as described in Japanese Patent Application No. 10-239148 (1998) (hereinafter referred to as literature 2), for example. In relation to the mobility &mgr; and the saturation velocity Vsat, however, there is known no method of performing extraction in a form matching with the remaining parameters.
In relation to the mobility &mgr;, for example, the Moneda method is generally known as a typical extraction method. The Moneda method is disclosed in F. H. De La Moneda, H. N. Kothcha and M. Shatzkes, “Measurement of MOSFET Constants”, IEEE Elect. Dev. Lett., EDL-3(1), pp. 10, 1982 (hereinafter referred to as literature 3). In the Moneda method, the following equation (1) is assumed as the model of the mobility &mgr;:
μ
=
μ0
1
+
θ
⁡
(
Vgs
-
Vth
)
(
1
)
where Vgs represents a gate-to-source voltage, &mgr;
0
represents the mobility &mgr; at the time when the gate-to-source voltage Vgs matches with the threshold voltage Vth, and &thgr; represents a parameter.
In this case, the total resistance Rtot is given by the following equation (2):
Rtot
=
Rds
+
S
⁡
(
θ
+
1
Vgs
-
Vth
-
Vds
/
2
)
(
2
)
where the parameter S is given by the following equation (3):
S
=
Lm
-
DL
μ0
·
Cox
·
Weff
(
3
)
where the parameter Cox is the capacitance of the gate insulator film OX.
On the basis of the equation (2), the mobility &mgr; is extracted along the following procedure:
Step 1: Drain-source current Ids vs. gate-to-source voltage Vgs characteristics (Ids−Vgs characteristics) in a linear region of a plurality of transistors (MOSFETs) different only in channel length from each other are measured.
Step 2: An Rtot−1/(Vgs−Vth−Vds/2) characteristic is plotted for each transistor as shown in
FIG. 33
, for performing linear fitting. Vds represents a drain-to-source voltage. In this case, slope of the straight line corresponds to S in the equation (3), and the vertical axis intercept is &thgr;·S+Rds (=R).
Step 3: From the result in the step 1, an S−Lm characteristic is plotted as shown in
FIG. 34
, for performing linear fitting. In this case, slope of the straight line is 1/(&mgr;
0
·Cox·Weff) (=C).
Step 4: Assuming that Wm≈Weff and Cox=&egr;ox/Tox, &mgr;
0
is given by Tox/(C·&egr;ox·Wm) from the result in the step 3, where &egr;ox represents a factor of proportionality between the capacitance Cox and 1/Tox. An actual value may be given to Cox.
Step 5: An R−S characteristic is plotted as shown in
FIG. 35
from the result in the step 1, for performing linear fitting. In this case, slope of the straight line is &thgr;.
In the Moneda method, as hereinabove described, primary deterioration is assumed in relation to the mobility &mgr;, for extracting the channel shortening DL, the external resistance Rds and the parameters &mgr;
0
and &thgr; related to the mobility &mgr; at the time when the gate-to-source voltage Vgs is around the threshold voltage Vth. Hence, a secondary mobility deterioration factor or external resistance Rds having Vgs dependency cannot be extracted.
This also applies to a well-known extraction method related to the velocity saturation effect. In a conventional typical method extracting a parameter related to the saturation effect, the following equation (4) is employed:
1
β0
=
Leff
+
U1
·
Vds
μ0
·
Cox
·
Weff
(
4
)
wher

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