Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2002-03-11
2004-04-27
Cuneo, Kamand (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S719000
Reexamination Certificate
active
06727724
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a characteristic evaluation method for insulated gate type transistors which extracts their effective channel widths, a characteristic evaluation apparatus for insulated gate type transistors, a method of manufacturing insulated gate type transistors by using the above characteristic evaluation method, and a computer readable storing medium storing a characteristic evaluation program.
2. Description of the Background Art
An electrically effective channel width, i.e., an effective channel width W
eff
, can be determined from the drain currents of two or more insulated gate type transistors having the same channel length and a different channel width. This method is generally called “drain current method.” The drain current method can directly determine the difference between an effective channel width W
eff
and a mask channel width W
m
, namely, a channel narrowing DW(=W
m
−W
eff
).
As a drain current method, a wide variety of methods have been proposed heretofore. They are described, for example, in “A New Method to Electrically determine Effective MOSFET Channel Width” by Y. R. Ma and K. L. Wang, IEEE Trans. Elect. Dev., ED-29, p. 1825, 1982; “A New Method to Determine the MOSFET Effective Channel Width” by N. D. Arora, L. A. Blair and L. M. Richardson, IEEE Trans. Elect. Dev., ED-37(3), p. 811, 1990; “A Method to Extract Gate-Bias-Dependent MOSFET's Effective Channel Width” by Y. T. Chia and G. J. Hu, IEEE Trans. Elect. Dev., ED-38(2), p. 424, 1991; and “A Direct Method to Extract Effective Geometries and Series Resistances of MOS Transistors” by P. R. Karlsson and K. O. Jeppson, Proc. IEEE ICMTS, vol. 7, p. 184, 1994.
Of various drain current methods, Chia method is commonly often used. Thus, Chia method will be briefly described here. The total source-drain resistance R is given by the sum of a channel resistance R
ch
and an external resistance R
sd
. Now, supposing the following Equation 1 as the equation to express drain current.
I
ds
=
β
0
·
(
V
gs
-
V
th
-
V
ds
*
2
)
·
V
ds
*
1
+
θ1
·
(
V
gs
*
-
V
th
)
+
θ
2
·
(
V
gs
*
-
V
th
)
2
(
Eq
.
1
)
where &bgr;
0
, V
ds
* and V
gs
* are given by the following Equations 2, 3 and 4, respectively, and &thgr;1 and &thgr;2 are the invariables.
β
0
=
μ
0
C
ox
W
eff
L
eff
(
Eq
.
2
)
where &mgr;
0
is a carrier mobility, L
eff
is an effective channel length, W
eff
is an effective channel width, and C
ox
is a gate insulating film capacity.
V
ds
*
=
V
ds
-
I
ds
·
R
sd
(
Eq
.
3
)
V
gs
*
=
V
gs
-
I
ds
·
R
sd
2
(
E
q
.
4
)
Neglecting the term of &thgr;2, Equation 5 is obtained from Equations 1, 3 and 4. Supposing an external resistance R
sd
is inversely proportional to an effective channel width W
eff
, a channel narrowing DW can be extracted through the following procedure.
I
ds
=
β
0
·
(
V
gs
-
V
th
-
V
ds
2
)
·
V
ds
1
+
(
θ1
+
β
0
·
R
sd
)
·
(
V
gs
-
V
th
)
(
Eq
.
5
)
where the difference between a gate voltage and a threshold voltage, (V
gs
−V
th
), is defined as a gate overdrive V
gt
.
Step 1: Against a certain gate overdrive V
gt
, I
ds
−W
m
characteristic is plotted in an X-Y plane whose X-axis is mask channel W
m
and Y-axis is drain current I
ds
, and a linear fitting is made. At that time, the intersection with the X-axis in the X-Y plane which is obtained by extrapolating each straight line is the channel narrowing DW (V
gt
) in the gate overdrive V
gt
(see FIG.
1
).
Step 2: By repeating step 1 while changing the gate overdrive V
gt
, it can be seen how the channel narrowing DW (V
gt
) depends on the gate overdrive V
gt
(see FIG.
1
).
Prior art characteristic evaluation method for insulated type transistors is constructed as described. In Chia method, for example, it is necessary to know the threshold voltage of a transistor for use in extraction. The threshold voltage of a transistor is found by, for example, extrapolation from the characteristic between gate voltage and source-drain current, as shown in FIG.
2
. Therefore, the error due to the uncertainty of a threshold voltage is further pronounced with reducing transistor size.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention, a characteristic evaluation apparatus for insulated gate type transistors in which at least two insulated gate type transistors that differ from each other only in mask channel width are used for evaluation and the characteristic of a first insulated gate type transistor having a wide mask channel width serves as a reference, to evaluate the characteristic of a second insulated gate type transistor having a narrow mask channel width. This apparatus comprises: a threshold voltage estimation means that extracts the threshold voltage of the first transistor, estimates the threshold voltage of the second transistor, and employs a value as estimated, as a first estimated value; an extraction means in which (i) a difference between a gate voltage of the first transistor and the extracted threshold voltage of the first transistor is defined as a first gate overdrive, and a difference between a gate voltage of the second transistors and the first estimated value is defined as a second gate overdrive, (ii) in an X-Y plane whose X-axis is the mask channel width and Y-axis is source-drain conductance, a virtual point at which a change of Y coordinate value is estimated to be approximately zero when the first and second gate overdrives are finely changed, is extracted from a characteristic curve exhibiting a relationship between the mask channel widths of the first and second transistors and the source-drain conductance, (iii) values of the X coordinate and Y coordinate at the virtual point are defined as second and third estimated values, respectively, and (iv) a slope of the characteristic curve at the virtual point is extracted and a value of the slope is employed as a fourth estimated value; a threshold voltage determination means in which (i) from the second to fourth estimated values, optimum second to fourth estimated values are found with which the change of the third estimated value is equal to the product of the change of the second estimated value and the fourth estimated value, in reply to fine changes of the first and second gate overdrives, (ii) an optimum first estimated value is determined which corresponds to the optimum second to fourth estimated values, and (iii) a true threshold voltage of the second transistor is determined based on the optimum first estimated value; and a channel narrowing determination means that determines a difference between the mask channel width and an effective channel width, based on the true threshold voltage.
According to a second aspect, the characteristic evaluation apparatus of the first aspect is characterized in that the extraction means approximates the characteristic curve by using a first straight line in the X-Y plane, the first straight line passing through a first point that is given to the first transistor when the first gate overdrive has a first value and a second point that is given to the second transistor when the second gate overdrive has the first value.
According to a third aspect, the characteristic evaluation apparatus of the second aspect is characterized in that the threshold voltage determination means determines the optimum second to fourth estimated values from a relational expression:
F
(
δ
,
V
gtWi
)
=
dW
**
(
δ
,
V
gtWi
)
+
f
(
δ
,
V
gtWi
)
f
′
(
δ
,
V
gtWi
)
·
dW
**
′
(
δ
,
V
gtWi
)
-
DW
*
(
δ
,
V
gtWi
)
where &dgr; is a difference between an estimated value of the threshold voltage of the second transistor, i.e., a first estimated value, and the threshold voltage of the
Kobert Russell M.
Oblon, Spiviak, McClelland, Maier & Neustadt, P.C.
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