Chapter mode selection apparatus for MOS memory

Details Chapter mode selection apparatus for MOS memory Chapter mode selection apparatus for MOS memory

1989-03-10

1991-09-10

Moffitt, James W.

Static information storage and retrieval

Addressing

Byte or page addressing

36523003, 36523008, 364200, 364900, G11C 800, G06F 1206

Patent

active

050479890

ABSTRACT:
An EPROM includes an on chip circuitry for selecting an alternative chapter mode addressing scheme. By utilizing the chapter addressing mode, a plurality of devices can be coupled in parallel, wherein each device is treated as a chapter of the total memory capacity. Hard latches are used to store a designated code and soft latches are used to latch in chapter addresses from data lines. A chapter is evaluated if values stored in the hard latch match the values inputted to the soft latch.

REFERENCES:
patent: 4368515 (1983-01-01), Nielsen
patent: 4685084 (1987-08-01), Canepa
patent: 4719598 (1988-01-01), Stockton
patent: 4864542 (1989-10-01), Oshima et al.

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