Channel ordering for communication signals split for matrix...

Multiplex communications – Communication techniques for information carried in plural... – Combining or distributing information via time channels

Reexamination Certificate

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C370S386000, C370S395430, C370S468000, C359S016000

Reexamination Certificate

active

06801548

ABSTRACT:

CROSS-REFERENCES TO RELATED APPLICATIONS
This application is related to patent application Ser. No. 09/477,166, filed Jan. 4, 2000, and entitled “METHOD AND APPARATUS FOR A REARRANGEABLY NON-BLOCKING SWITCHING MATRIX,” having A. N. Saleh, D. E. Duschatko and L. B. Quibodeaux as inventors. This application is assigned to Cisco Technology, Inc., the assignee of the present invention, and is hereby incorporated by reference, in its entirety and for all purposes.
This application is related to patent application Ser. No. 09/232,395, filed Jan. 15, 1999, and entitled “A CONFIGURABLE NETWORK ROUTER,” having H. M. Zadikian, A. N. Saleh, J. C. Adler, Z. Baghdasarian, and V. Parsi as inventors. This application is assigned to Cisco Technology, Inc., the assignee of the present invention, and is hereby incorporated by reference, in its entirety and for all purposes.
This application is related to patent application Ser. No. 09/608,097 having attorney docket no. M-8321 US filed Jun. 30, 2000, and entitled “CONCATENATION DETECTION ACROSS MULTIPLE CHIPS,” having Douglas E. Duschatko, Lane Byron Quibodeaux, Robert A. Hall, Andrew J. Thurston as inventors. This application is assigned to Cisco Technology, Inc., the assignee of the present invention, and is hereby incorporated by reference, in its entirety and for all purposes.
This application is related to patent application Ser. No. 09/607,912 having attorney docket no. M-8320 US filed Jun. 30, 2000, and entitled “PATH AIS INSERTION FOR CONCATENATED PAYLOADS ACROSS MULTIPLE CHIPS,” having Douglas E. Duschatko, Lane Byron Quibodeaux, Robert A. Hall, Andrew J. Thurston as inventors. This application is assigned to Cisco Technology, Inc., the assignee of the present invention, and is hereby incorporated by reference, in its entirety and for all purposes.
This application is related to patent application Ser. No. 09/609,577 having attorney docket no. M-8209 US filed Jun. 30, 2000, and entitled “FIXED ALGORITHM FOR CONCATENATION WIRING,” Vahid Parsi and Andrew J. Thurston as inventors. This application is assigned to Cisco Technology, Inc., the assignee of the present invention, and is hereby incorporated by reference, in its entirety and for all purposes.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to data communications, and, more particularly, efficiency in data communication circuits.
2. Description of the Related Art
A data communications network is the interconnection of two or more communicating entities (i.e., data sources and/or sinks) over one or more data links. A data communications network allows communication between multiple communicating entities over one or more data communications links. High bandwidth applications supported by these networks include streaming video, streaming audio, and large aggregations of voice traffic. In the future, these demands are certain to increase. To meet such demands, an increasingly popular alternative is the use of lightwave communications carried over fiber optic cables. The use of lightwave communications provides several benefits, including high bandwidth, ease of installation, and capacity for future growth.
The synchronous optical network (SONET) protocol is among those protocols designed to employ an optical infrastructure and is widely employed in voice and data communications networks. SONET is a physical transmission vehicle capable of transmission speeds in the multi-gigabit range, and is defined by a set of electrical as well as optical standards.
In some networks, network nodes store data which they use for proper operation. In SONET, data between adjacent nodes are transmitted in modules called STS's (synchronous transport signals). Each STS is transmitted on a link at regular time intervals (for example, 125 microseconds). See Bellcore Generic Requirements document GR-253-CORE (Issue 2, December 1995) incorporated herein by reference. An STS-1 is a defined as a specific sequence of 810 bytes (6480 bits) including overhead bytes and an envelope capacity for transporting payloads. An STS-N frame is a sequence of N×810 bytes wherein N is a predetermined number. An STS-N is formed by byte-interleaving of STS-1 and STS-M modules, wherein M is less than N.
Ordering communication channels for STS-N signals entering a switching matrix using standard SONET multiplexing order requires level 1 switching (STS-1 type switching). Level 1 switching is complicated and is an inefficient way to switch signals. What is needed is a non-standard SONET multiplexing order that does not require level 1 switching and that allows efficient switching of the STS-N signals.
SUMMARY OF THE INVENTION
The present invention provides a non-standard SONET multiplexing order that does not require level 1 switching and that allows efficient switching of STS-N signals. This ordering of communication channels allows an STS-N signal to be processed by a selected STS-N pointer processor ASIC.
Pointer processing and matrix switching are simplified using the channel ordering method. STS-1 level switching is not required. The invention allows an STS-N signal from an OC line card to be communicated without requiring reordering of STS-N signals by the switching matrix.
According to an embodiment, an apparatus and method for a synchronous optical network (SONET) includes ordering a plurality of signals of a first type in one or more line cards for transmit to one or more types of line cards, wherein the ordering of the first type of signals creates a plurality of independent signals of a second type, and transmitting the plurality of the first type of signals to the one or more types of line cards, wherein the independence of the signals of the second type permits the one or more types of line cards to be in an arbitrary order. The permitting the one or more types of line cards to be in an arbitrary order eliminates a need to reorder the plurality of the first type of signals in a switching matrix. A method according to an embodiment includes demultiplexing the plurality of signals of the first type in a switching matrix, wherein the demultiplexing is independent of reducing the plurality of signals of the first type to a basic module, such as a synchronous transport signal at level 1.
According to a further embodiment, the method includes matching the plurality of the first type of signals from the line card to one or more types of line cards in a predetermined order, the one or more types of line cards adapted to receive one or more types of signals.
In an embodiment, the method is for the plurality of signals of the first type, synchronous transport signals (STS) having N modules (STS-N), wherein the ordering includes assigning to a variable A a number of basic modules on the one or more line cards,assigning to a variable B a number of processors adapted for STS-N signals on the one or more line cards, calculating a variable C by dividing A by B, C being the number of basic module channels common to each of the processors, calculating a variable D by dividing C by three, D being a number of contiguous channels, dividing each STS-N signal into N/D portions, each portion including up to D bytes, and for each portion of the STS-N signal, selecting one of the number of processors adapted for STS-N signals, and transmitting the portion of the STS-N signal to the one of the number of processors.


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