Data processing: database and file management or data structures – Database design – Data structure types
Reexamination Certificate
1999-07-06
2002-01-08
Shah, Sanjiv (Department: 2172)
Data processing: database and file management or data structures
Database design
Data structure types
C707S793000
Reexamination Certificate
active
06338054
ABSTRACT:
BACKGROUND OF THE INVENTION
1) Field of the Invention
The present invention relates to a technique applied when a plurality of processing apparatuses share a plurality of file storing apparatuses through a file controlling apparatus. In particular, the present invention relates to a method for controlling re-connection of a channel interface between a processing apparatus and a file controlling apparatus due to generation of a re-connecting factor, after the channel interface has been temporarily made to be in a disconnected state since the processing apparatus cannot access to the file storing apparatus when accessing to the file storing apparatus, and a file controlling apparatus for realizing the above method.
2) Description of the Related Art
When a plurality of processing apparatuses share a plurality of file storing apparatuses, there is generally provided, between between the processing apparatuses and the file storing apparatuses, a file controlling apparatus which controls an accessing operation on each file storing apparatus in response to a command from each processing apparatus. The processing apparatus is, for example, a CPU, whereas the file storing is, for example, a device (DASD: Direct Access Storage Device) such as a magnetic disk or the like. Hereinafter, the file controlling apparatus will be referred as an FCU, whereas the file storing apparatus will be referred simply as a device, occasionally.
In a system having the above FCU, a CPU locks out an access from another CPU by a reserve command in order to read data from each device shared by other CPUs or write data in the device, then issues a read command or a write command when an occupancy of the device is established.
The FCU is a shared device. When a certain CPU occupies the device, the FCU thereafter reports device busy to a command from another CPU to disconnect that CPU. When the device is released from the occupied state by a release command from the CPU having issued the reserve command, the FCU re-connects the CPU (channel) to which device busy has been reported (device end interruption due to release: a first re-connecting factor).
When a read command process or a write command process involves an operation (staging operation) of the magnetic disk, the FCU disconnects a CPU having issued a read command or a write command, then re-connects the CPU (channel) when the staging operation of the magnetic disk is completed (device end interruption due to staging completion: a second re-connecting factor). Incidentally, the staging operation is to read data from a device holding the data into a cache memory when the data to be read or to be written does not exist in the cache memory in the FCU.
Now, a structure of a general FCU will be described with reference to FIG.
23
.
FIG. 23
is a block diagram showing a structure of a general FCU. As shown in
FIG. 23
, the FCU
1
is provided between CPUs
2
-
0
and
2
-
1
and devices
3
-
0
through
3
-
2
in order that a plurality (two in
FIG. 23
) of the CPUs
2
-
0
and
2
-
1
share a plurality (three in
FIG. 23
) of the devices
3
-
0
through
3
-
2
to control an access operation on each of the devices
3
-
0
through
3
-
2
in response to a command from each of the CPUs
2
-
0
and
2
-
1
. Incidentally, when either one of the two existing CPUs is specified, a reference character
2
-
0
or
2
-
1
is used, or when there is no need to specify, a reference character
2
is used. Similarly, when any one of the three existing devices is specified, a reference character
3
-
0
,
3
-
1
or
3
-
2
is used, or when there is no need to specify, a reference character
3
is used.
The FCU
1
comprises CAs (Channel Adapter)
11
-
0
through
11
-
3
, an RM (Resource Manager)
12
, a TS (Table Storage)
13
, a CFE (Cache Function Engine)
14
, a cache memory
15
, DAs (Device Adapter)
16
-
0
through
16
-
2
, a command bus
17
and a data bus
18
. Incidentally, when any one of the four existing CAs is specified, a reference character
11
-
0
,
11
-
1
, . . . or
11
-
3
is used, or when there is no need to specify, a reference character
11
is used. Similarly, when any one of the three existing DAs is specified, a reference character
16
-
0
,
16
-
1
or
16
-
2
is used, or when there is no need to specify, a reference character
16
is used.
Each of the CAs
11
-
0
through
11
-
3
is a module in charge of control on an interface with a corresponding CPU
2
-
0
or
2
-
1
via a channel interface. Each of the CPUs
2
-
0
and
2
-
1
has, for example, two channels (CH)
2
a
and
2
b.
In an example shown in
FIG. 23
, channels
2
a
and
2
b
of the CPU
2
-
0
are connected to the CAs
11
-
0
and
11
-
1
, respectively. Channels
2
a
and
2
b
of the CPU
2
-
1
are connected to the CAs
11
-
2
and
11
-
3
, respectively.
The RM
12
is a module in charge of resource management with respect to a basic operation. The TS
13
is a memory used as a table for resource management. The RM
12
and the TS
13
function as a controlling unit for controlling re-connection of a channel interface due to generation of a re-connecting factor, after a channel interface with one of the two CPUs
2
-
0
and
2
-
1
is temporarily made to be in a disconnected state since the CPU
2
cannot access to one of the three devices
3
-
0
,
3
-
1
or
3
-
2
when the CPU
2
accesses to the device
3
, as will be described with reference to
FIGS. 24 through 46
.
The CFE
14
is a module in charge of management of the cache memory
15
. Each of the DAs
16
-
0
through
16
-
2
is a module in charge of control on an interface with a corresponding device
3
-
0
,
3
-
1
or
3
-
2
such as a magnetic disk or the like.
The command bus
17
is used to exchange commands among the CA
11
, the RM
12
, the CFE
14
and the DA
16
. The data bus
18
is used to exchange data among the CA
11
, the CFE
14
, the cache memory
15
and the DA
16
.
Next, functional structures of the RM
12
and the TS
13
controlling re-connection of a channel interface will be described with reference to
FIGS. 24 through 29
.
FIG. 24
is a block diagram showing a functional structure of a general RAM
12
/TS
13
.
FIGS. 25 through 29
are diagrams illustrating a reserve management table
31
, a device busy report management table
32
, a device end report management table
33
, a task control block (TCB)
34
and a staging completion report management table (queue)
35
.
As shown in
FIG. 24
, the TS
13
holds the reserve management table
31
, the device busy report management table
32
, the device end report management table
33
, the TCB
34
and the staging completion report management table
35
. The RM
12
functions as a mechanism (re-connecting mechanism due to device release) executing a re-connecting process using the device busy report management table
32
and the device end report management table
33
of the TS
13
when the above first re-connecting factor generates. The RM
12
also functions as a mechanism (re-connecting mechanism due to staging completion) executing a re-connecting process using the staging completion report management table
35
of the TS
13
when the above second re-connecting factor generates.
The reserve management table
31
is configured as shown in
FIG. 25
to manage a device
3
occupied by a CPU
2
. Incidentally, in the table
31
, “CA0” through “CA3” correspond to the CA
11
-
0
through the CA
11
-
3
, respectively, and device numbers
0
through
2
correspond to the devices
3
-
0
through
3
-
2
, respectively. For example, when a reserve command for the device
3
-
0
is issued from the channel
2
a
of the CPU
2
-
0
so that the CPU
2
-
0
can occupy the device
3
-
0
, the RM
12
sets “1” at the intersection of “CA0” and device number
0
in the table
31
(refer to FIG.
36
).
The device busy report management table
32
is configured as shown in
FIG. 26
to manage a CPU
2
to which the RM
12
reports device busy through a corresponding CA
11
, and a device
3
that the CPU
2
intends to occupy. Incidentally, in the
Fujitsu Limited
Shah Sanjiv
Staas & Halsey , LLP
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