Channel interface circuit with high speed data message header fi

Details Channel interface circuit with high speed data message header fi Channel interface circuit with high speed data message header fi

1981-06-22

1984-01-03

Smith, Jerry

Boots, shoes, and leggings

G06F 304

Patent

active

044245653

ABSTRACT:
The subject channel interface circuit functions in a multiprocessor environment to provide a high speed interface between a processor and the communication channel which interconnects all the processors. The communication channel carries data messages, which messages contain a header field specifying source, destination and control information. The subject channel interface circuit is programmable and serves to dynamically translate the header portion of the data message as it is received and thereby determine whether this data message is to be stored in the processor memory. If the data message is to be stored, the channel interface circuit immediately converts the header field into a hardware address, which is used to activate a specific location in processor memory. The data message is then inputted (via DMA) to this memory location and the appropriate buffer pointers are reset. Thus, the subject channel interface circuit performs all the data receiving tasks, including message storage and linking, without requiring the involvement of the associated processor.

REFERENCES:
patent: 3588831 (1971-06-01), Figueroa et al.
patent: 4092715 (1978-05-01), Scriver
patent: 4093981 (1978-06-01), McAllister et al.
patent: 4133030 (1979-01-01), Huettner et al.
patent: 4156907 (1979-05-01), Rawlings et al.
patent: 4189769 (1980-02-01), Cook et al.
patent: 4225919 (1980-09-01), Kyu et al.
patent: 4228496 (1980-10-01), Katzman et al.
Electronic Design 12, Jun. 7, 1979, "Data Communications Part Three", pp. 98-104, Alan J. Weissberger.
The 8086 Family User's Manual, Oct. 1979, "8237/8237-2, High Performance Programmable DMA Controller", pp. B-92 to B-105.
Peripheral Design Handbook, Feb. 1978, "8257/8257-5, Programmable DMA Controller", pp. 1-72 to 1-88.

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