Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2005-09-06
2005-09-06
Lam, David (Department: 2827)
Static information storage and retrieval
Floating gate
Particular connection
C365S185110, C365S200000
Reexamination Certificate
active
06940754
ABSTRACT:
A channel erase flash memory including a redundancy word line group constituted of a plurality of redundancy word lines separately from a normal memory space of a memory cell array, and including a function of replacing the normal word line group including a defective memory cell with the redundancy word line group. In the memory, at the time of an erase operation, a first voltage is applied to a well region in which the memory cell array is formed, a second voltage of 0 V or less is applied to a normal word line, and a third voltage is applied to all the word lines included in the normal word line group including the defective memory cell or the redundancy word line group. A potential difference between the first and third voltages is set to be smaller than that between the first and second voltages.
REFERENCES:
patent: 6215699 (2001-04-01), Yamamoto
patent: 07-320496 (1995-12-01), None
Toru Tanzawa et al., “A 44-mm2Four-Bank Eight-Word Page-Read 64-Mb Flash Memory With Flexible Block Redundancy and Fast Accurate Word-Line Voltage Controller”, IEEE Journal of Solid-State Circuits, vol. 37, Nov. 11, 2002, pp 1485-1492.
Hogan & Hartson LLP
Kabushiki Kaisha Toshiba
Lam David
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