Channel driving circuit of virtual channel DRAM

Details Channel driving circuit of virtual channel DRAM Channel driving circuit of virtual channel DRAM

2001-05-25

2002-09-03

Nelms, David (Department: 2818)

Static information storage and retrieval

Interconnection arrangements

C365S208000, C365S230060, C365S230080

Reexamination Certificate

active

06445604

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a virtual channel DRAM, and in particular to an improved virtual channel DRAM which can improve cell efficiency, reduce a layout area of a chip and increase a data processing speed, by unifying a data processing method.
2. General Description and Related Art
FIG. 1
(Prior Art) is a schematic diagram of a channel structure of a conventional virtual channel DRAM. The virtual channel DRAM includes: sixteen channel block units
100
_
0
~
100
_
15
respectively consisting of four unit channel units
110
~
140
for temporarily storing all or part of a set of data electrically connected to a bit line according to an active command; and sixteen channel control units
20
_
0
~
20
_
15
connected to one sides of the sixteen channel block units
100
_
0
~
100
_
15
, for controlling the four unit channel units
110
~
140
. 128 normal channel registers
1
and four redundancy channel registers
2
are consecutively positioned in the respective unit channel units
110
~
140
. The 128 normal channel registers
1
are connected to one another through a channel read bus
3
, and the four redundancy channel registers
2
are connected to one another through a redundancy channel read bus
4
. The 128 normal channel registers
1
and the four redundancy channel registers
2
are connected to each other through a channel write bus
5
.
Read type I/O data bus connectors
6
and write type I/O data bus connectors
7
are connected between the channel control units
20
_
0
~
20
_
15
and the normal channel registers
1
. The read type I/O data bus connectors
6
are respectively connected between the channel read bus
3
and data bus sense amp units
41
,
43
,
45
,
47
, and the write type I/O data bus connectors
7
are respectively connected between the channel write bus
5
and write driver units
51
~
54
. Redundancy type I/O data bus connectors
8
are respectively connected between the redundancy channel read bus
4
and redundancy data bus sense amp units
42
,
44
,
46
, and
48
.
In addition, the data bus sense amp units
41
,
43
,
45
, and
47
sense and amplify data output through the channel read bus
3
in a read operation and stored in the normal channel registers
1
, and output them to a global read data bus grd. The redundancy data bus sense amp units
42
,
44
,
46
, and
48
sense and amplify data outputt through the redundancy channel read bus
4
in the read operation and stored in the redundancy channel registers
2
, and output them to the global read data bus grd.
The write driver units
51
~
54
drive a data inputted through a global write data bus gwd in a write operation, and output them to the write type I/O data bus connectors
7
. And the virtual channel DRAM has column decoding units
131
~
134
for receiving column address signals through column address bus lines. The column decoding units
131
~
134
receive column address signals through the column address bus lines and selects column lines of a normal channel register
62
and a redundancy channel register
64
of the unit channel units
210
~
240
in a read or a write operation.
However, in the conventional virtual channel DRAM, the read type and write type I/O data bus connectors
6
,
7
are connected to one channel control unit
20
_
0
~
20
_
15
, thereby occupying a large layout area. In addition, the data bus sense amp units used in the read operation are divided into the normal type and redundancy type, thereby increasing power consumption as well as the layout area.
Moreover, in the unit channels
110
~
140
, the 128 normal channel registers
1
and the redundancy channel registers
2
are connected through the channel write bus
5
. Accordingly, a load is increased in the read operation, and thus a data processing speed is reduced.
SUMMARY
The claimed inventions feature, at least in part a virtual channel DRAM which can improve cell efficiency, reduce a layout area of a chip and increase a data processing speed, by unifying a data processing method.
There is provided a virtual channel DRAM including: a plurality of channel block units consisting of first to fourth unit channel units where a plurality of normal channel registers and a plurality of redundancy channel registers are commonly connected through one local data bus. A plurality of I/O data bus connectors are respectively connected between the local data bus of the unit channel units and global data buses. A plurality of channel control units are respectively connected to one sides of the plurality of channel block units, for controlling the operation of the first to fourth unit channel units. A plurality of data bus sense amp units are respectively connected between the global data buses and a global read data bus, for sensing input data in a normal read operation and a redundancy operation. A plurality of write driver units respectively connected between the global data buses and a global write data bus, for driving input data.
Some of the claimed inventions feature a virtual channel DRAM including a plurality of channel block units respectively consisting of first to fourth unit channel units. A plurality of normal channel registers and a plurality of redundancy channel registers are divided into halves at the right and left sides, and are respectively connected in series through a local data bus. A plurality of I/O data bus connectors are respectively connected between the local data bus of the unit channel units and global data buses. A plurality of channel control units are respectively connected to one sides of the plurality of channel block units, for controlling the operation of the first to fourth unit channel units. A plurality of data bus sense amp units are connected between the global data buses and a global read data bus one by one, for sensing input data in a normal read operation and a redundancy operation. A plurality of write driver units are respectively connected between the global data buses and a global write data bus, for driving input data.


REFERENCES:
patent: 5469388 (1995-11-01), Park
patent: 6144577 (2000-11-01), Hidaka
patent: 6233181 (2001-05-01), Hidaka

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