Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2008-07-08
2008-07-08
Phan, Trong (Department: 2827)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185270, C365S185280, C365S185290
Reexamination Certificate
active
11190722
ABSTRACT:
A post-erase channel clearing procedure for double well, floating gate, non-volatile memory cells. The channel is cleared of charged particles coming from the floating gate after an erase operation in two steps. In the first step the charged particles are pushed into an upper substrate well below the floating gate but not allowed into a deeper well of opposite conductivity type relative to the upper well. After a brief time, T, the charged particles are pushed by a bias voltage into the deeper well from the upper well. This two step clearing procedure avoids device latchup that might occur otherwise.
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Atmel Corporation
Phan Trong
Schwegman Lundberg & Woessner, P.A.
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