1986-03-14
1989-09-19
James, Andrew J.
357 13, 357 43, 357 20, 357 59, H01L 2972
Patent
active
048686247
ABSTRACT:
A monolithic semiconductor transistor structure is described wherein the active collector region of a bipolar-junction transistor is physically and operatively merged with the channel region of a junction field-effect transistor, providing a composite circuit which approximates a cascode configuration. By controlling the integral of the net impurity doping concentration to various active regions of the device, the active collector region of a bipolar-junction transistor configuration is made sufficiently thin so as to simultaneously function as an active collector region as well as a channel region of one or more field-effect transistors. The channel-collector transistor provides high breakdown voltage, high dynamic resistance and linearity over a wide voltage range, and is compatible with solid-state batch fabrication processes for direct incorporation into larger integrated circuits. The device is particularly suitable for linear applications. Improved operating current is obtained and current limiting constraints of the device are minimized by cooperative emitter and base configurations, topologically extended to maximize use of available circuit area. Interdigitated base and collector region layout further improves operating performance.
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Hamilton et al, Basic Integrated Circuit Engineering, McGraw-Hill, N.Y., 1975, pp. 21-24.
Sze, Physics of Semiconductor Devices, 1st Edition (Wiley, N.Y., 1969), p. 43.
Warner, Jr. and Grung, "A Bipolar Lock Layer Transistor", Solid-State Electronics, 18, 323 (1975).
Grung Bernard L.
Warner, Jr. Raymond M.
Zipperian Thomas E.
James Andrew J.
Regents of the University of Minnesota
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