Channel CODEC processor configurable for multiple wireless...

Pulse or digital communications – Transceivers

Reexamination Certificate

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C375S220000, C375S222000

Reexamination Certificate

active

10040727

ABSTRACT:
A reconfigurable channel CODEC (encoder and decoder) processor for a wireless communication system is disclosed. A high degree of user programmability and reconfigurability is provided by the channel CODEC processor. In particular, the reconfigurable channel CODEC processor includes processor cores and algorithm-specific kernels that contain logic circuits tailored for carrying out predetermined but user-configurable decoding and encoding algorithms. The interconnects between the processor cores and the algorithm-specific kernels are also user-configurable. Thus, the same hardware can be reconfigured for many different wireless communication standards.

REFERENCES:
patent: 5181209 (1993-01-01), Hagenauer et al.
patent: 5406570 (1995-04-01), Berrou et al.
patent: 5446747 (1995-08-01), Berrou
patent: 5485486 (1996-01-01), Gilhousen et al.
patent: 5513176 (1996-04-01), Dean et al.
patent: 5519761 (1996-05-01), Gilhousen
patent: 5533011 (1996-07-01), Dean et al.
patent: 5537444 (1996-07-01), Nill et al.
patent: 5559865 (1996-09-01), Gilhousen
patent: 5563897 (1996-10-01), Pyndiah et al.
patent: 5594718 (1997-01-01), Weaver, Jr. et al.
patent: 5603096 (1997-02-01), Gilhousen et al.
patent: 5621752 (1997-04-01), Antonio et al.
patent: 5625876 (1997-04-01), Gilhousen et al.
patent: 5657420 (1997-08-01), Jacobs et al.
patent: 5680395 (1997-10-01), Weaver et al.
patent: 5691974 (1997-11-01), Zehavi et al.
patent: 5697055 (1997-12-01), Gilhousen et al.
patent: 5715236 (1998-02-01), Gilhousen et al.
patent: 5721745 (1998-02-01), Hladik et al.
patent: 5721746 (1998-02-01), Hladik et al.
patent: 5729560 (1998-03-01), Hagenauer et al.
patent: 5734962 (1998-03-01), Hladik et al.
patent: 5748650 (1998-05-01), Blaker et al.
patent: 5751761 (1998-05-01), Gilhousen
patent: 5761248 (1998-06-01), Hagenauer et al.
patent: 5778338 (1998-07-01), Jacobs et al.
patent: 5812938 (1998-09-01), Gilhousen et al.
patent: 5822318 (1998-10-01), Tiedemann, Jr. et al.
patent: 5841806 (1998-11-01), Gilhousen et al.
patent: 5848063 (1998-12-01), Weaver, Jr. et al.
patent: 5859612 (1999-01-01), Gilhousen
patent: 5864760 (1999-01-01), Gilhousen et al.
patent: 5905900 (1999-05-01), Combs et al.
patent: 5917812 (1999-06-01), Antonio et al.
patent: 5933787 (1999-08-01), Gilhousen et al.
patent: 5943361 (1999-08-01), Gilhousen et al.
patent: 5970413 (1999-10-01), Gilhousen
patent: 6014411 (2000-01-01), Wang
patent: 6081229 (2000-06-01), Soliman et al.
patent: 6085349 (2000-07-01), Stein
patent: 6111865 (2000-08-01), Butler et al.
patent: 6141781 (2000-10-01), Mueller
patent: 6157668 (2000-12-01), Gilhousen et al.
patent: 6185246 (2001-02-01), Gilhousen
patent: 6205190 (2001-03-01), Antonio et al.
patent: 6239748 (2001-05-01), Gilhousen
patent: 6304612 (2001-10-01), Baggen et al.
patent: 6353640 (2002-03-01), Hessel et al.
patent: 6381457 (2002-04-01), Carlsson et al.
patent: 6434203 (2002-08-01), Halter
patent: 2001/0008837 (2001-07-01), Takahashi
patent: 2001/0009850 (2001-07-01), Kushige
patent: 2001/0013854 (2001-08-01), Ogoro
patent: 2001/0018735 (2001-08-01), Murakami et al.
patent: 2001/0022787 (2001-09-01), Mchale
patent: 2001/0023395 (2001-09-01), Su et al.
patent: 2001/0024173 (2001-09-01), Katz
patent: 2001/0024433 (2001-09-01), Vanttinen
patent: 2001/0025242 (2001-09-01), Joncour
patent: 2001/0027544 (2001-10-01), Joncour
patent: 2001/0038663 (2001-11-01), Medlock
patent: 2001/0041536 (2001-11-01), Hasegawa
patent: 2001/0046211 (2001-11-01), Maruwaka et al.
patent: 2001/0047427 (2001-11-01), Lansio et al.
patent: 2001/0048713 (2001-12-01), Medlock et al.
patent: 2001/0051506 (2001-12-01), Riikonen
patent: 2002/0015401 (2002-02-01), Subramanian et al.
patent: 2002/0031166 (2002-03-01), Subramanian et al.
Arrigo et al., “Adaptive FEC on a Reconfigurable Processor for Wireless Multimedia Communications, Circuits and Systems”. ISCAS '98. Proceedings of the1998 IEEE International Symposium, vol. 4, pp. 417-420.
Halter et al., “Reconfigurable Signal Processor for Channel Coding & Decoding in Low SNR Wireless Communications”,IEEE Workshop on Signal Processing Systems 1998, Oct. 8-10, 1998, pp. 260-274, especially pp. 260-262 and 266-273.
Phillips, L., et al.; “A Baseband IC for 3G UMTS Communications”; Proc. of Vehicular Technology Conference, Amsterdam, Netherlands, vol. 3, Sep. 19, 1999, pp. 1521-1524.
Verbauwhede, Ingrid, et al.; “Low Power DSP's for Wireless Communications”; Proc. of International Symposium on Low Power Electronics and Design Islped, Rapallo, Italy, Jul. 26, 2000, pp. 303-310.
Weinsziehr, Dirk, et al.; “KISS-16V2: A One-Chip ASIC DSP Solution for GSM”: IEEE Journal of Solid-State Circuits, vol. 27, No. 7, Jul. 1992, pp. 1057-1065.
Telecommunications and Mission Operations Directorate—DSN Technology Program,“Communications System Analysis: Turbo Codes.” http://www331.jpl.nasa.gov/public/TurboForce.GIF; Date Accessed: Dec. 27, 2001; pp. 1.

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