Pulse or digital communications – Multilevel – Disparity reduction
Reexamination Certificate
2000-03-09
2001-03-27
Pham, Chi H. (Department: 2631)
Pulse or digital communications
Multilevel
Disparity reduction
C375S259000, C341S055000, C341S058000, C341S068000
Reexamination Certificate
active
06208697
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a channel code converter, to a channel coding system therefor, and to a recording medium recording an encoding control program. The present invention is particularly adapted to digital recording disk devices such as an optical disk device, a magnet-optic disk device, a phase-change disk device and a hard disk device, and to a digital recording VTR (video tape recorder).
2. Description of the Prior Art
In a digital recording disk device, digital data are recorded in a digital form not directly but after the data are encoded. This also applies to recording video and audio data in a digital form in the digital recording VTR. A representative example of a channel code used in encoding the data may be a (1,7) code.
FIG. 1
shows a code conversion table of the (1, 7) code. In
FIG. 1
, two data bits are converted into 3 channel bits, and are then recorded according to an NRZI (non-return to zero inverse) rule.
FIG. 1
further illustrates an example of recording according to the NRZI rule after 4 data bits are converted into 6 channel bits. The NRZI rule is the one in which a bit is inverted with “1” and is recorded, and a bit is not inverted with “0” and is recorded.
The (1, 7) code may cause deviation in the decoded pattern due to an error at the time of recording/reproduction. By taking the return of this case into consideration, a synchronization signal is inserted every after several hundred to several thousand bits. The synchronization signal uses a channel bit pattern that does not appear in the normal data to make a clear distinction over the data.
Characteristics of the channel code are generally evaluated in terms of a minimum inversion interval Tmin, a maximum inversion interval Tmax, a detection window width Twin, and a DC (direct-current) component. It is desired that the minimum inversion interval Tmin is great and (Tmax/Tmin) is small. It is further desired that the detection window width is great and the DC component is free or is small as much as possible.
The (1, 7) code has a minimum inversion interval Tmin=1.33T, a maximum inversion interval Tmax=5.33T, a detection window width Twin=0.67T, and the DC component which is not free. The (1, 7) code has an advantage in that the minimum inversion interval Tmin and the detection window width Twin are large, and the maximum inversion interval Tmax has a normal value. However, the (1, 7) code has a defect in that the DC component is not free. As described above, a suitable channel code is required for a recording system which requires free DC.
SUMMARY OF THE INVENTION
It is therefore an object of this invention to provide a channel code converter which increases a minimum inversion interval as large as possible, decreases (Tmax/Tmin) as small as possible, increases the detection window width as large as possible, and decreases the DC component as small as possible.
Concretely speaking, the invention provides a channel code converter in which Tmin=1.33T, Tmax=5.33T, Twin=0.67T and which is capable of decreasing the DC component as much as possible.
Another object of this invention is to provide a channel coding system suited for the above channel code converter.
A further object of the invention is to provide a recording medium recording an encoding control program for the above channel coding system.
A channel code converter of the present invention includes a table unit for storing the combinations of channel bits of a bit number larger than a predetermined bit number assigned by the combinations of data bits of a predetermined bit number. The channel code converter converts codes of data bits of the predetermined bit number into channel bits by using the table unit and, then, records the data according to an NRZ (non-return to zero) rule.
The table unit includes a first table for storing data that satisfy predetermined conditions. The data satisfying the predetermined conditions are those data having a pattern in which the same bits are continuing by not less than 2 bits in the head portion and in the last portion among the patterns in which the same bits are necessarily continuing by not less than 2 bits except in the head portion and in the last portion of the data stored in the table unit among the channel bits, the same bits necessarily continuing by not more than k bits (k is a positive integer) except in the head portion and in the last portion, and the same bits are continuing by not more than (k−1) bits in the head portion and in the last portion. The table unit further includes a second table for storing the data of a pattern in which the head portion starts with either “01” or “10” and the same bits are continuing by not less than 2 bits in the last portion among the patterns in which the bits are continuing by not more than (k−1) bits. The table unit further includes a third table for storing the data in which the same bits are continuing by not less than 2 bits in the head portion, and the last portion ends with “01” and “10” among the patterns in which the bits are continuing by not more than (k−1) bits. The table unit further includes a fourth table for storing the data of a pattern in which the head portion starts with either “01” or “10” and the last portion ends with either “01” or “10” among the patterns in which the bits are continuing by not more than (k−1) bits.
The channel code converter further includes a selection unit for selecting any one of the first table to the fourth table so as to start with a channel bit data same as the final bit of one channel bit before and so as to end with a channel bit data same as the start bit of one channel bit after. The channel code converter so works that the continuing data bits of a data stream converted inclusive of a connection portion between the channel bits are not smaller than 2 bits but are not larger than k bits.
A channel coding system according to the present invention records the data by using the above channel code converter. The channel coding system includes a step for selecting any one of the first table to the fourth table so as to start with a channel bit data same as the final bit of one channel bit before and to end with a channel bit data same as the start bit of one channel bit after.
A recording medium according to the present invention records an encoding control program to have the channel code converter record the data. The encoding control program causes the channel code converter to select any one of the first table to the fourth table so as to start with a channel bit data same as the final bit of one channel bit before and to end with a channel bit data same as the start bit of one channel bit after. The encoding control program further so works that the continuing data bits of a data stream converted inclusive of a connection portion between the channel bits are not smaller than 2 bits but are not larger than k bits.
The channel code converter of the present invention converts 16 data bits into 24 channel bits, and record the data in the form of NRZ in an optical disk device or in the like device. In the channel code converter, the number of the continuing bits of the same code is selected to be from 2 to 8 bits to impart the same characteristics as the (1, 7) code, and the total number of data in which the continuing bits are two bits is set to be not larger than i bits (i is a positive integer) in 24 bits to select an optimum table out of the four tables to stably lock the PLL (phase-locked loop). Thus, Tmin=1.33T, Tmax=5.33T and Twin=0.67T are realized, and the DC component can be decreased as small as possible.
REFERENCES:
patent: 4520346 (1985-05-01), Shimada
patent: 4598267 (1986-07-01), Fukuda
patent: 5198813 (1993-03-01), Isozaki
patent: 5469162 (1995-11-01), Chaki et al.
patent: 5870040 (1999-02-01), Ando
Hayes Soloway Hennessey Grossman & Hage PC
NEC Corporation
Pham Chi H.
Phu Phuong
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