Channel check test system

Details Channel check test system Channel check test system

2001-08-07

2002-12-24

Tieu, Binh (Department: 2643)

Telephonic communications

Diagnostic testing, malfunction indication, or electrical...

C379S022020, C379S027010, C379S028000, C370S242000, C370S247000, C370S250000

Reexamination Certificate

active

06498833

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a channel check test system for checking the continuity of a channel in digital circuit multiplication equipment (hereinafter called “DCME”).
BACKGROUND ART
The DCME is known as an equipment for transmitting a voice signal over a telephone communication line with high efficiency using low rate encoding technique and a digital speech interpolation technique. In this DCME, a channel check test for checking existence or nonexistence of the continuity of a transmission channel is made.
A conventional channel check test system will be explained with reference to the drawings.
FIG. 12
is a diagram showing the structure of the conventional channel check test system.
In
FIG. 12
, reference numerals
1
and
2
respectively designate a transmitting side DCME and a receiving side DCME. Reference numeral
3
designates an input signal nonlinear-quantized by an A-law or a &mgr;-law and inputted to the transmitting side DCME
1
. An input pattern generator
4
generates an input test pattern nonlinear-quantized by the A-law or the &mgr;-law. An A-law input pattern data memory
4
a
stores input test pattern data nonlinear-quantized by the A-law. A &mgr;-law input pattern data memory
4
b
accumulates input test pattern data nonlinear-quantized by the &mgr;-law. Reference numeral
4
c
designates a selector. A test pattern insertion circuit
5
inserts an output signal of the input pattern generator
4
into a channel to be tested. An encoder
6
encodes an output signal of the test pattern insertion circuit
5
with high efficiency.
In this figure, a decoder
7
decodes the encoded signal. Reference numerals
8
a
and
8
b
respectively designate a decoded signal nonlinear-quantized by the A-law or the &mgr;-law and outputted from the decoder
7
, and an output signal nonlinear-quantized by the A-law or the &mgr;-law from the receiving side DCME
2
. An output pattern generator
9
generates an output test pattern nonlinear-quantized by the A-law or the &mgr;-law. An A-law output pattern data memory
9
a
stores output test pattern data nonlinear-quantized by the A-law. A &mgr;-law output pattern data memory
9
b
stores output test pattern data nonlinear-quantized by the &mgr;-law. Reference numeral
9
c
designates a selector. A comparator
10
compares the decoded signal
8
a
and the output test pattern. A counter
11
counts the number of conformity bits of the output test pattern and the decoded signal
8
a
. A judging circuit
12
judges existence or nonexistence of the continuity of a channel on the basis of an output of the counter
11
. Reference numeral
13
designates judged results. Reference numerals
14
a
,
14
b
,
14
c
and
14
d
designate companding law setting signals.
An operation of the above-mentioned conventional channel check test system will next be explained with reference to the drawings.
The operation of the conventional channel check test system with respect to an operated channel which is not being tested, i.e., a channel for transmitting a voice talking signal will first be explained.
An input signal
3
inputted to the transmitting side DCME
1
is provided to the encoder
6
without inserting the input test pattern into this signal in the test pattern insertion circuit
5
and is encoded with high efficiency. Output data of the encoder
6
are outputted to the receiving side DCME
2
.
The input signal
3
is a PCM signal nonlinear-quantized by the A-law or the &mgr;-law prescribed in ITU Recommendation G.711. When a companding law of the nonlinear quantization of the input signal
3
is the A-law, the companding law setting signal
14
b
is provided such that an operating mode of the encoder
6
is set to the A-law. In contrast to this, when the companding law of the input signal
3
is the &mgr;-law, the companding law setting signal
14
b
is provided such that the operating mode of the encoder
6
is set to the &mgr;-law.
In the receiving side DCME
2
, the received output data of the encoder
6
are decoded in the decoder
7
, and are outputted as an output signal
8
b
from the receiving side DCME
2
. The output signal
8
b
from the receiving side DCME
2
is also a PCM signal nonlinear-quantized by the A-law or the &mgr;-law. The companding law setting signal
14
c
is provided, and an operating mode of the decoder
7
is set such that the output signal
8
b
from the receiving side DCME
2
is set to a predetermined companding law (the A-law or the &mgr;-law).
The operation of the conventional channel check test system with respect to the channel which is being tested will next be explained.
The input pattern generator
4
generates an input test pattern for checking the channel. The test pattern insertion circuit
5
outputs this input test pattern instead of the input signal
3
inputted to the transmitting side DCME
1
to the encoder
6
. The encoder
6
encodes the input test pattern with high efficiency, and output data of the encoder
6
are outputted to the receiving side DCME
2
.
It is necessary to set the companding law of the input test pattern outputted from the input pattern generator
4
in conformity with the companding law of the encoder
6
. Therefore, one of output data of the A-law input pattern data memory
4
a
and output data of the &mgr;-law input pattern data memory
4
b
is selected in the selector
4
c
in accordance with a companding law setting signal
14
a
and is made to be an output signal of the input pattern generator
4
.
In the receiving side DCME
2
, the received output data of the encoder
6
are decoded in the decoder
7
. Each bit of a decoded signal
8
a
outputted from this decoder
7
is compared with the corresponding bit of an output signal of the output pattern generator
9
in the comparator
10
. Output data of the output pattern generator
9
should be an expected pattern of the decoded signal obtained by firstly encoding the output signal of the input pattern generator
4
and secondly re-decoding this encoded signal.
It is necessary to set the companding law of the output test pattern outputted from the output pattern generator
9
in conformity with the companding law of the decoder
7
. Therefore, one of output data of the A-law output pattern data memory
9
a
and the &mgr;-law output pattern data memory
9
b
is selected in the selector
9
c
in accordance with a companding law setting signal
14
d
and is made to be an output signal of the output pattern generator
9
.
Compared results of each bit outputted from the comparator
10
are inputted to the counter
11
and this counter
11
counts the number of nonconformity bits within a predetermined time. The counted number of nonconformity bits outputted from the counter
11
is inputted to the judging circuit
12
. When the counted value exceeds a predetermined value, the judging circuit
12
judges that the continuity of the testing channel does not exist. In contrast to this, when the counted value does not exceed the predetermined value, the comparing circuit
12
judges that the continuity of the testing channel exists, and outputs results
13
of this judgment.
In the channel check test system constructed above, when plural coding systems (e.g., coding systems prescribed in ITU Recommendations G.726, G.728, G.729, etc.) are supported in the DCME, one of the solution for this case is to prepare an input test pattern and an output test pattern in accordance with the coding systems separately. However, when the input test pattern and the output test pattern are respectively prepared in accordance with the coding systems, a problem exists in that a circuit scale of the channel check test system is large-sized.
A system for checking continuity by using a tone signal as the input test pattern and monitoring a sign bit of an output of the decoder
7
within the receiving side DCME
2
is considered as a method able to be commonly used irrespective of the coding systems with a simple structure.
FIG. 13
is a diagram showing the structure of another conventional channel check test system shown

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