Channel change indication circuit with delayed memory activation

Details Channel change indication circuit with delayed memory activation Channel change indication circuit with delayed memory activation

1978-07-03

1979-08-21

Bookbinder, Marc E.

325468, H04B 126

Patent

active

041654897

ABSTRACT:
A limited-channel television tuning system includes a MNOS memory for storing tuning voltage information. Memory locations are addressed by channel address means through an encoder-decoder arrangement. The encoder supplies a clock-controlled channel address register for transferring the encoded address information to a comparator, which is also supplied directly with the encoded address information. The comparator outputs drive a delay circuit, consisting of a clocked flip flop AND gate arrangement, through a NOR gate. The output of the AND gate supplies a one-shot multivibrator for energizing the memory.

REFERENCES:
patent: 4131853 (1978-12-01), Dreiske

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