Channel apparatus having a plurality of channels capable of bein

Details Channel apparatus having a plurality of channels capable of bein Channel apparatus having a plurality of channels capable of bein

1993-09-16

1996-12-10

Lee, Thomas C.

Boots, shoes, and leggings

395841, 3642329, 3642463, 3642467, 3642513, G06F 1502

Patent

active

055840418

ABSTRACT:
A channel processor (CHP) within a channel apparatus instructs parallel transfer of data through a plurality of channels within a channel cluster (CCL), when it reads out a LCUW. Each of the channels sequentially generates addresses of a main storage determined based on numbers of respective channels under control of a control section and a channel data controller (CDC) accesses the main storage according to the generated addresses to read out data. Those channels transfer the data in parallel to an auxiliary storage device through an optical fiber cable set. This auxiliary storage device includes a plurality of channel ports, two buffer control circuits, a buffer and a high speed storage unit. The buffer has a two-face structure, each of the faces having 2 kilo-bytes. One of the buffer control circuits receives data from the channel ports through the optical fiber cable set in the plurality of channels and selects either one of the faces of the buffer to write them therein. As soon as all the received data are written in either one of the faces of the buffer, they are read out by the other of the buffer control circuits to be written in the high speed storage unit.

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"Enterprise Systems Architecture 390 ESCON I/O Interface (SA 22-7202)", pp. 3-2, 3-3, 6-6, published by IBM.
"IBM ESA/390 Principles of operation (SA-7201)", pp. 14-13, 14-14, 15-25, published by IBM.

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