Changeable decoder structure for a folded logic array

Details Changeable decoder structure for a folded logic array Changeable decoder structure for a folded logic array

1975-11-06

1977-06-14

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

235152, 307241, 307DIG5, 328 92, H03K 1920, G06F 900, H03K 1300

Patent

active

040299708

ABSTRACT:
This specification describes a decoder for a programmable logic array (PLA) having opposite ends of input lines of the array connected to outputs of different decoders. Previously two-bit decoders were arranged on opposite sides of the array to generate input variables from two sets of two different input signals each and feed those input variables to four input lines. Here, instead of using two-bit decoders, four one-bit decoders are positioned on each side. The outputs of these one-bit decoders are programmable to change the connections between them and the input lines of the array. The arrangement permits the decoders to perform one-bit, two-bit decoding on signals on the same side of the input lines, to do two-bit decoding on signals on opposite sides of the array and in combination with other sets of decoders to do three and four-bit decoding of input signals.

REFERENCES:
patent: 3816725 (1974-06-01), Greer
patent: 3829846 (1974-08-01), Berg et al.
patent: 3849638 (1974-11-01), Greer
patent: 3936812 (1976-02-01), Cox et al.
Howley et al., "Programmable Logic Array Decoding Technique"; IBM Tech. Discl. Bull., vol. 17, No. 10, p. 2988, Mar. 1975.

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