Electric heating – Heating devices – Combined with container – enclosure – or support for material...
Reexamination Certificate
1998-02-25
2001-03-13
Walberg, Teresa (Department: 3742)
Electric heating
Heating devices
Combined with container, enclosure, or support for material...
C438S905000, C134S001100, C118S724000
Reexamination Certificate
active
06201219
ABSTRACT:
BACKGROUND OF THE INVENTION
1. The Field of the Invention
The present invention relates to the etching and deposition of materials on in-process integrated circuit semiconductor substrates, such as silicon wafers. More particularly, the present invention relates to the cleaning of processing chambers within which etching and deposition of materials takes place on in-process integrated circuit wafers.
2. The Relevant Technology
The competitive computer and electronics industry is constantly striving to produce more powerful products at lower prices. One area within this industry which is rapidly progressing is the development of very large scale (VLSI) and ultra large scale (ULSI) integrated circuits. These integrated circuits are being made in increasingly smaller and more integrated scales, and the processes by which they are manufactured are developing to keep up with the pace. These processes, which are continually evolving in the attempt to miniaturize integrated circuits and lower production costs, include etching and deposition operations on in-process integrated circuit wafers or semiconductor substrates from which the integrated circuits are derived.
In the context of this document, the term “semiconductor substrate” is defined to mean any construction comprising semiconductive material, including but not limited to bulk semiconductive material such as a semiconductive wafer, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials. The term “substrate” refers to any supporting structure including but not limited to the semiconductor substrates described above.
Specifically, one problem which slows down integrated circuit development processes is the removal of deposited material that forms on exposed surfaces of processing chambers during etching and deposition operations on the in-process integrated circuit wafers. In processes such as reactive ion etching (RIE), magnetically enhanced reactive ion etching (MRIE), ion bombardment etching, chemical vapor deposition (CVD), and physical vapor deposition (PVD), the processing chambers in which these operations are conducted unavoidably incur depositions of the etched or deposited materials. The deposited material typically comprises, for example, metals such as aluminum or tungsten, polymer materials from photoresist masking materials, or other materials that are etched from or deposited on the in-process integrated circuit wafers. If not removed, the deposited material will scale, eventually peel off, and fall on the in-process integrated circuit wafers, damaging them.
Newer methods of deposition are now being developed which are more selective and confine the deposits to smaller areas. One example of such a process is a low temperature cold wall CVD process. Nevertheless, even these more selective processes require periodic halts in production to clean buildups of material from the vicinity of the wafer and the equipment on which the wafer is held.
The process conventionally used for removing buildups of material from processing chamber walls is reactive plasma cleaning. In reactive plasma cleaning processes, a plasma is struck in the processing chamber by creating an electrical bias and passing a species source gas such as chlorine, for example, into the electrical bias. The source gas is ionized by collisions with electrons, a plasma is struck thereby, and the ions are accelerated with the electrical bias and strike the exposed surfaces in the processing chamber.
A problem associated with reactive plasma cleaning is that the plasma is indiscriminate and etches all exposed surfaces in the processing chamber, including the processing chamber walls. Many of these surfaces do not incur depositions of material, and their lifetime is prematurely reduced by the plasma cleaning which etches into the surfaces.
Furthermore, the selection of materials from which the processing chamber walls can be made is limited. For instance, if aluminum is being etched or deposited in the processing chamber, a build up of aluminum will occur which must be cleaned, and an etchant for aluminum is typically selected. If the processing chamber walls were constructed of aluminum, however, the cleaning process would rapidly etch into the aluminum walls and eventually cause harm to the processing chamber walls. Consequently, the prior art is limited in the choice of materials for constructing processing chamber walls that can be utilized. Furthermore, even if none of the materials which are deposited and cleaned are the same as the material used for constructing the processing chamber walls, premature wear on the processing chamber walls still typically occurs.
From the above discussion, it can be seen that a new process for cleaning processing chambers is needed in order to increase the throughput of VLSI and ULSI integrated circuit manufacturing where chambers for etching and deposition processes are used. A process is also needed which overcomes the prior art problems of scaling, excessive wear, and inherent limitations in the material of which the processing chamber walls can be formed.
SUMMARY OF THE INVENTION
The present invention seeks to resolve the above and other problems which have been experienced in the art. More particularly, the present invention constitutes an advancement in the art by providing processes for cleaning processing chambers. In accordance with the invention as embodied and broadly described herein in the preferred embodiment, a process is provided for the cleaning of a processing chamber. Also provided is a modified processing chamber in which selected surfaces thereof can be cleaned so as to realize an improved throughput of wafers for the processing chamber.
The modifications to the processing chamber which enable the selective cleaning involve a device for bombarding surfaces with a bombarding species within the enclosed processing chamber, and a device for applying a temperature pattern to a predetermined portion of the bombarded surfaces within the processing chamber. The device for bombarding causes the removal of the built up material deposited on the predetermined portion of the bombarded surfaces, where the built up material is a result of prior operations conducted within the processing chamber. The device for bombarding typically comprises heat driven plasma cleaning, by which species, such as ions, are bombarded upon the inside surface to selectively etch the surfaces which have been heated by the temperature pattern. The species bombardment can be conducted with active or neutral gas species, such as an ion source gas. Alternatively, a reactive species can be created remote from the chamber and then transported into the chamber. The reactive species, once within the chamber, begins to bombard inside surfaces of the chamber that have been heated in a predetermined temperature pattern.
The device for applying a temperature pattern can be of any construction such that energy is applied to exposed surfaces in a predetermined temperature pattern. Three general embodiments are disclosed herein. In various embodiments, the temperature pattern is applied with the use of flame emitting nozzles, or with the use of lamps which are directed to the selected surfaces which have received deposits of material. Multiple lamps can be used, and the lamps can be of different intensities and can be set at different power levels in order to better customize the temperature pattern.
In a further general embodiment, heating elements are embedded in the predetermined portion of the bombarded surfaces which receive greater deposits of material. The heating elements can be arranged in particular patterns and can also be varied in heat output and power levels in order to better select the surfaces which have received greater deposits of material.
A third general embodiment comprises the use of a susceptor located at or near the predetermined portion of the bombarded surfaces which have received deposits of the material. The susceptor
Iyer Ravi T.
Sandhu Gurtej S.
Westmoreland Donald L.
Fuqua Shawntina
Micro)n Technology, Inc.
Walberg Teresa
Workman & Nydegger & Seeley
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