Chalcogenide memory device with multiple bits per cell

Details Chalcogenide memory device with multiple bits per cell Chalcogenide memory device with multiple bits per cell

2005-01-04

2005-01-04

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Bulk effect device

Bulk effect switching in amorphous material

C257S002000, C257S003000, C257S005000

Reexamination Certificate

active

06838692

ABSTRACT:
A memory device with multiple bits per-cell. The memory device includes a side electrode; a doped semiconductor region disposed laterally in contact with a sidewall of the side electrode, such that the doped semiconductor region forms a diode, or the junction between the side electrode and the doped semiconductor region forms a diode; a layer of phase-changing material disposed laterally in contact with a sidewall of the doped semiconductor region, such that the doped semiconductor region is disposed between the layer of phase-changing material and the side electrode; and an upper electrode disposed on the layer of phase-changing material. Many storage regions can be stacked vertically, and multiple bits can be stored in one cell. Also, the contact area is reduced to a minimum dimension below the photolithographic limit.

REFERENCES:
patent: 5166758 (1992-11-01), Ovshinsky et al.
patent: 5296716 (1994-03-01), Ovshinsky et al.
patent: 5789758 (1998-08-01), Reinberg
patent: 6114713 (2000-09-01), Zahorik
patent: 6147395 (2000-11-01), Gilgen
patent: 6189582 (2001-02-01), Reinberg et al.

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