Electrical computers and digital processing systems: processing – Architecture based instruction processing
Reexamination Certificate
2011-01-11
2011-01-11
Kim, Kenneth S (Department: 2111)
Electrical computers and digital processing systems: processing
Architecture based instruction processing
C712S019000
Reexamination Certificate
active
07870366
ABSTRACT:
The present disclosure provides an architecture that enables massive parallel processing on an IC while alleviating control congestion, memory access congestion and wiring congestion, together with high flexibility where the processing units are soft-arranged to perform different tasks. In an embodiment, the present architecture includes a functional block with a GO component to start the functional block, and a DONE component to identifying the completion status. The GO and DONE components can be linked together, preferably by a linkage component, to chain the functional blocks. The linkage is preferably soft configurable. In another embodiment, the present architecture includes an integrated circuit comprises a plurality of functional blocks chained together for serial processing, parallel processing, or any combination thereof.
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Kulkarni Raj
Mitra Hirak
Moon Michael
Wicks Richard
Kim Kenneth S
Nguyen Tue
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