Chained arbitration

Details Chained arbitration Chained arbitration

1994-10-28

1996-09-17

Harvey, Jack B.

395730, 395848, G06F 13368

Patent

active

055577563

ABSTRACT:
A bus arbitration circuit, having a state machine which receives a processor request signal, a request signal from each of a group of internal input/output devices, and an external device request signal. The state machine sends a processor grant signal, a grant signal to one of the internal devices, or a grant signal to the external device, as each of the devices receives control of the bus. The circuit has a signal inverter connected to the processor request signal and another signal inverter connected to the processor grant signal. A control signal controls whether or not the inverters invert the signals. When multiple arbitration circuits are cascaded, the processor request and grant signals are not inverted for the primary bus arbitration circuit, but the request and grant signals are inverted for all secondary bus arbitration circuits.

REFERENCES:
patent: 4641266 (1987-02-01), Walsh
patent: 4779089 (1988-10-01), Theus
patent: 5168568 (1992-12-01), Thayer et al.
patent: 5179705 (1993-01-01), Kent
patent: 5301282 (1994-04-01), Amini et al.
patent: 5381538 (1995-01-01), Amini et al.

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